industry news
Subscribe Now

Tortuga Logic and Cadence® Collaborate to Deliver Radix-M™ Firmware Security Validation Platform on Palladium® Z1

Joint Offering Provides the First Automated Security Validation Solution to Identify Vulnerabilities in Firmware and System-on-Chip (SoC) Designs

SAN JOSE, Calif.May 29, 2019 /PRNewswire/ — Tortuga Logic, a cybersecurity company specializing in hardware threat detection and prevention, today announced the launch of Radix-M™, the industry’s first platform capable of performing security validation of firmware on complex system-on-chip (SoCs) designs. Built with funding support from the Defense Advanced Research Projects Agency (DARPA), Radix-M identifies and prevents unknown firmware vulnerabilities. It also automates previously manual processes firmware engineers and SoC security teams conduct using the existing hardware- and cloud-based Cadence® Palladium® Z1 Enterprise Emulation Platform for seamless hardware and software execution.

“Engineering teams spend tremendous time and effort validating their firmware and chip designs, yet the methods can sometimes pose challenges when it comes to detecting security vulnerabilities,” said Paul Cunningham, Corporate VP and GM of the Systems and Verification Group at Cadence Design Systems. “Cadence collaborated with Tortuga Logic on the development and use of Tortuga Logic’s Radix-M with our Palladium Z1 emulation platform by targeting firmware vulnerabilities in modern SoCs and reducing the risk of security exploits from reaching the field.”

The First Security Validation System at the Intersection of Firmware and Chip Designs
SoC design teams run emulation to ensure their firmware is operating correctly. Firmware sets hardware configuration parameters to ensure correct functionality. Traditionally, the only way to assess firmware security has been through a tedious, manual process that does not adequately identify vulnerabilities directly associated with the hardware, where the majority of exploits occur. In addition, product engineers largely rely on parameters set by security architects to secure their configurations, often resulting in a disconnect between the two teams that allows vulnerabilities to go unnoticed.

Radix-M addresses this critical market void by offering the first automated way to execute thorough security validation procedures for firmware and chip designs. When integrated with commercial emulation systems, such as the Cadence Palladium Z1 platform, Radix-M analyzes an entire software stack on the hardware, ensuring security simultaneously on both parts of the system.

“Systems can’t be secured unless you can identify vulnerabilities at the intersection of the firmware and hardware,” said Jason Oberg, CEO of Tortuga Logic. “Development teams often run ‘normal’ emulation to ensure their firmware operates correctly, for example making sure their chip boots. Radix-M is a huge value add that simultaneously supports firmware security during the actual execution of the real hardware. Security validation at this part of the process prevents firmware misconfigurations that leave SoCs vulnerable to security breaches.”

Available now, Radix-M represents the second product in Tortuga Logic’s industry-leading series of hardware-based security solutions, including Radix-S™, that address the broader need for complete firmware validation. For sales inquiries, contact

Tortuga Logic will demonstrate the Radix™ series June 3-5 at the 2019 Design Automation Conference (DAC), booth #827 in Las Vegas. To schedule a meeting at DAC, contact

About Tortuga Logic
Founded in 2014, Tortuga Logic is a cybersecurity company that provides industry-leading solutions to address security vulnerabilities overlooked in today’s systems. Tortuga Logic’s innovative hardware security verification platforms, Radix-S™ and Radix-M™, enable system-on-chip (SoC) design and security teams to detect and prevent system-wide exploits that are otherwise undetectable using current methods of security review. To learn more, visit or contact

Leave a Reply

featured blogs
May 27, 2020
Could life evolve on ice worlds, ocean worlds, ocean worlds covered in ice, halo worlds that are tidally locked with their sun, and rogue worlds without a sun? If so, what sort of life might it be?...
May 26, 2020
I get pleasure from good quality things. Quality is a vague term, but, to me, it is some combination of good design for usability, functionality and aesthetics, along with reliability and durability. Some of these factors can be assessed very quickly; others take time. For ex...
May 26, 2020
#robotcombat #combatrobots #robotwars #WeWantSeason5 #WeGotSeason5 These are some of the most popular hashtags used by a growing number of global BattleBots enthusiasts. Teams from all backgrounds design, build and test robots of all sizes for one purpose in mind: Robot Comba...
May 22, 2020
[From the last episode: We looked at the complexities of cache in a multicore processor.] OK, time for a breather and for some review. We'€™ve taken quite the tour of computing, both in an IoT device (or even a laptop) and in the cloud. Here are some basic things we looked ...

Featured Video

DesignWare 112G Ethernet PHY IP JTOL & ITOL Performance

Sponsored by Synopsys

This video shows the Synopsys 112G Ethernet PHY IP in TSMC’s N7 process passing the jitter and interference tolerance test at the IEEE-specified bit error rate (BER). The IP with leading power, performance, and area is available in a range of FinFET processes for high-performance computing SoCs.

Click here for more information

Featured Paper

Adaptive Beamformer: An HLS Optimization Case Study with SLX FPGA

Sponsored by Silexica

Learn more about how SLX FPGA provides a productivity and efficiency boost when using high-level synthesis (HLS) to implement FPGA applications in C/ C++, through automated analysis and optimization. In this beamforming example, SLX FPGA is able to achieve lower latency and cut development time from weeks down to minutes compared to hand-optimization for similar cost of resources.

Click here to download the whitepaper