industry news
Subscribe Now

Synopsys IC Compiler II Delivers First-Pass Silicon Success for Graphcore’s Multi-Billion Gate AI Processor

Innovative AI-Hardware Design Technologies Accelerate Time-to-Market for Second-Generation 7nm Colossus IPU

MOUNTAIN VIEW, Calif., Oct. 12, 2020 /PRNewswire/ —

Highlights

  • IC Compiler II, part of the Synopsys Fusion Platform, with its industry-leading capacity and throughput, accelerated implementation of the massive Colossus IPU, exceeding 59 billion transistors
  • Innovative optimization technologies for AI-hardware design in the Synopsys RTL-to-GDS flow delivered best-in-class performance, power and areas (PPA) metrics
  • Integrated golden signoff technologies delivered predictable and convergent design closure with a zero-margin flow

Synopsys, Inc. (Nasdaq: SNPS) today announced that Graphcore achieved first-pass silicon success using the industry-leading IC Compiler II place-and-route solution, part of the Synopsys Fusion Platform, for designing its second-generation Colossus MK2 GC200 Intelligence Processing Unit (IPU), featuring 59.4 billion transistors, on an industry-leading 7nm advanced process technology. Graphcore leveraged Synopsys IC Compiler II ultra-high capacity architecture and innovative technologies for AI-hardware design resulting in an accelerated implementation of their massive AI processor. Synopsys’ RTL-to-GDS flow with state-of-the-art power optimization capabilities along with embedded golden signoff technologies like PrimeTime® delay calculator, provided Graphcore design teams superior out-of-the-box PPA metrics, and the fastest design closure.

“Synopsys’s digital full-flow solution with its best-in-class RTL-to-GDS tools, including Design Compiler® and IC Compiler II, offers the most comprehensive single-vendor platform, critical to the on-schedule tape out of our latest Colossus IPU,” said Phil Horsfield, vice president of Silicon at Graphcore. “Our long-standing relationship with Synopsys has enabled us to leverage state-of-the-art technologies from IC Compiler II and exceed the performance/power targets of this advanced AI processor. We are confident that continued collaboration with Synopsys on IC Compiler II and Fusion Compiler will enable us to push the boundaries of machine intelligence compute.”

The second-generation Colossus GC200 IPU from Graphcore is a sophisticated chip, integrating 1,472 independent processor cores and more than 900 megabytes of on-chip memory to deliver superior parallel processing power for data-center scale AI applications. Synopsys’ IC Compiler II, with its AI-design focused capabilities, includes top-level interconnect planning, logic restructuring, congestion-driven mux optimization and full-flow concurrent clock and data optimization delivers best-in-class PPA for the highly repetitive, MAC-based topologies typical in complex AI accelerator chips. Further, its native, high-capacity data model with adaptive abstraction and distributed implementation can efficiently handle multi-billion instance designs with quick turn-around-time. With a unique, golden signoff engine backbone, IC Compiler II delivers highest correlation and hyper-convergent design, to further accelerate design turnaround time.

“The design complexity boundaries of AI compute are continuing to be pushed to its limits, such as with Graphcore’s introduction of its latest Colossus IPU,” said Neeraj Kaul, vice president of Engineering, Design Group at Synopsys. “Its success in leveraging the latest, AI-optimized technologies in IC Compiler II to simultaneously meet the multiple aggressive design targets for their most complex chip reinforces our leadership position as the place-and-route tool of choice for next-generation, AI designs.”

Learn more details about this complex AI Chip as Phil Horsfield, vice president of Silicon at Graphcore, will be presenting on October 14 at the upcoming Synopsys Digital Design Technology Symposium.  For more information regarding Synopsys products, visit: https://www.synopsys.com/implementation-and-signoff.html.

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software partner for innovative companies developing the electronic products and software applications we rely on every day. As the world’s 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you’re a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.

Leave a Reply

featured blogs
May 14, 2021
Another Friday, another week chock full of CFD, CAE, and CAD news. This week features a topic near and dear to my heart involving death of the rainbow color map for displaying simulation results.... [[ Click on the title to access the full blog on the Cadence Community site....
May 13, 2021
Samtec will attend the PCI-SIG Virtual Developers Conference on Tuesday, May 25th through Wednesday, May 26th, 2021. This is a free event for the 800+ member companies that develop and bring to market new products utilizing PCI Express technology. Attendee Registration is sti...
May 13, 2021
Our new IC design tool, PrimeSim Continuum, enables the next generation of hyper-convergent IC designs. Learn more from eeNews, Electronic Design & EE Times. The post Synopsys Makes Headlines with PrimeSim Continuum, an Innovative Circuit Simulation Solution appeared fi...
May 13, 2021
By Calibre Design Staff Prior to the availability of extreme ultraviolet (EUV) lithography, multi-patterning provided… The post A SAMPle of what you need to know about SAMP technology appeared first on Design with Calibre....

featured video

Insights on StarRC Standalone Netlist Reducer

Sponsored by Synopsys

With the ever-growing size of extracted netlists, parasitic optimization is key to achieve practical simulation run times. Key trade-off for any netlist reducer is accuracy vs netlist size. StarRC Standalone Netlist reducer provides the flexibility to optimize your netlist on a per net basis. The user has total control of trading accuracy of some nets versus netlist optimization - yet another feature from StarRC to provide flexibility to the designer.

Click here for more information

featured paper

Compact. Precise. Connected. Increase productivity with intelligent edge computing.

Sponsored by Texas Instruments

Smart devices in factories and buildings are getting smaller and more capable, with enhanced real-time control, robust connectivity, and configurable web services. Read about new processor technology that is unleashing the true potential of Industry 5.0 and the Internet of Things.

Click here to read more

featured chalk talk

PCI Express: An Interconnect Perspective

Sponsored by Samtec

New advances in PCIe demand new connectors, and the challenge of maintaining signal integrity has only gotten tougher. In this episode of Chalk Talk, Amelia Dalton chats with Matthew Burns of Samtec about why PCIe isn’t just for PCs, what PCIe over fiber looks like, and how Samtec’s team of signal integrity experts can help with your next PCIe design.

Click here for more information about PCI Express® Solutions from Samtec