MOUNTAIN VIEW, Calif., Dec. 3, 2020 /PRNewswire/ —
Highlights:
- Collaboration includes multiple signoff domains and spans library characterization to full-chip signoff for accelerated design closure
- Signoff solution innovations address unique challenges from 5nm to 3nm to ensure signoff accuracy with 20X faster runtime and half the memory consumption
- Customer productivity enhanced by 5X reduction in ECO iterations and better hardware efficiency
Synopsys, Inc. (Nasdaq: SNPS) today announced that with its industry-leading, broad portfolio of golden signoff products, Synopsys has collaborated with Samsung Foundry to deliver a fully qualified flow with significant gains in accuracy, turnaround time and designer productivity. By targeting 5G, artificial intelligence and high-performance computing SoCs, these gains enable customers at Samsung 5-nanometer (nm) to 3nm process nodes to achieve optimal power, performance, area (PPA) and accelerate time-to-results (TTR).
“Samsung Foundry serves many leading-edge customers in the most advanced application segments that demand the highest levels of design performance, robustness, and power efficiency,” said Sangyun Kim, vice president of Foundry Design Technology at Samsung Electronics. “Our collaboration with Synopsys has been instrumental in delivering state-of-the-art signoff flows to our customers for our advanced 5 to 3nm process nodes.”
The Synopsys fully qualified signoff flow includes the following solutions:
- PrimeTime®: Supports ultra-low voltage variation, via variation and multi-input switching with 3% correlation to SPICE, 50 percent reduction in overall memory footprint and a 20X performance increase for path-based analysis
- StarRC™: Extraction with a 2X runtime improvement and accuracy within 1 percent of golden reference
- StarRC Field Solver: Deployed as the golden reference for advanced node enablement
- PrimeECO™: Enables 5X faster design closure, eliminating costly iterations between implementation and signoff
- PrimePower: Provides an 8X faster gate-level power analysis using RTL simulation vectors
- SiliconSmart®: Delivers 10X overall performance increase including enablement on Synopsys Cloud Service, significantly reducing the turnaround time for library characterization
“Collaborations with industry leaders in semiconductor design and manufacturing is at the core of our continued innovations in design signoff,” said Jacob Avidan, senior vice president of engineering in Synopsys’ Design Group. “We are fortunate to team up with Samsung Foundry to drive these innovations across a wide range of signoff technologies pushing performance limits and reducing margins required for design with the highest degree of confidence on Samsung’s latest advanced process technologies. We look forward to continuing our collaboration for the next wave of designs and application segments.”
The collaboration spans the broad portfolio of Fusion Design Platform™ signoff solutions, including PrimeTime static timing analysis, PrimeECO design closure, PrimePower power analysis, StarRC extraction and SiliconSmart library characterization.
For more information about Synopsys’ fully qualified signoff flow features optimized for Samsung Foundry 5/3nm process technologies, visit https://www.synopsys.
About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world’s 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you’re a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.
