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SmartDV Reduces Protocol Debug Time with Smart ViPDebug

New Protocol Debugger Rapidly Identifies Violations; Linked Waveform and Transaction Views Pinpoint Causes

SAN JOSE, CALIF –– May 16, 2019 –– SmartDV™ Technologies today unveiled Smart ViPDebug™, a protocol debugger that reduces debug time by rapidly identifying violations and reducing the time needed to find the cause of violations through its linked waveform and transaction database views.

Smart ViPDebug will be demonstrated continuously at the 56th Design Automation Conference (DAC) in the SmartDV Booth (#514) June 3 through June 5 at the Las Vegas Convention Center in Las Vegas, Nev.

“Improved system-level verification approaches are fundamental for addressing the complexity of on-chip interfaces and communication protocols,” says Deepak Kumar Tala, managing director of SmartDV, the Proven and Trusted choice for Verification intellectual property (IP). “A fast, smart, configurable and intuitive protocol debugger will enable verification engineers to work more efficiently, reducing time and effort.”

Adding Smart to Protocol Debug

System-on-chip (SoC) designs integrate a variety of design IP blocks, each with different interfaces and communication protocols, making the verification of the different blocks and their interactions a challenge. Functionally verifying the communications and protocols both within an SoC and its external interfaces to the system is a major undertaking of time and resources for verification engineering groups.

Smart ViPDebug reduces the time spent debugging communications protocols during the verification process by rapidly identifying violations. It fully encapsulates protocol specifications by eliminating the need for in-depth protocol knowledge and links a visual waveform display with a transaction log for swift discovery of violations and causes. Smart ViPDebug works across SmartDV’s broad portfolio of smart and configurable Verification IP solutions.

Features include a linked waveform viewer and a tabulated transaction view that are searchable and sortable. An error detection mode highlights violations in the waveform display and log file. The mode can be set to show as errors or warnings.

SmartDV at Design Automation Conference

SmartDV will demonstrate Smart ViPDebug™ and feature its smart Verification IP solutions at DAC in booth #514 Monday, June 3, through Wednesday, June 5, from 10 a.m. until 6 p.m.

DAC attendees can schedule demonstrations through SmartDV’s online scheduler.

Pricing and Availability

Smart ViPDebug will begin shipping in July.

Pricing is available upon request.

About SmartDV

SmartDV™ Technologies is the Proven and Trusted choice for Verification and Design IP with the best customer service from more than 250 experienced ASIC and SoC design and verification engineers. Its high-quality standard or custom protocol Verification and Design IP is compatible with all verification languages, platforms and methodologies supporting all simulation, emulation and formal verification tools used in a coverage-driven chip design verification flow. The result is Proven and Trusted Verification and Design IP used in hundreds of networking, storage, automotive, bus, MIPI and display chip projects throughout the global electronics industry. SmartDV is headquartered in Bangalore, India, with U.S. headquarters in San Jose, Calif. Visit www.Smart-DV.com to learn more.

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