industry news
Subscribe Now

SmartDV Delivers First-to-Market MIPI A-PHY v1.0 Verification IP

Firmly Establishes SmartDV, its Proven and Trusted Verification IP in the Automotive Market Segment

SAN JOSE, CALIF. –– September 22, 2020 –– SmartDV™ Technologies once again is the first company to ship Verification intellectual property (IP) to support MIPI A-PHY v1.0, the industry-standard, long-reach serializer-deserializer (SerDes) physical layer interface, delivering it as the MIPI Alliance announced availability.

MIPI A-PHY v1.0’s asymmetric long-reach physical layer interface forms the cornerstone of  the MIPI Automotive SerDes Solutions (MASS) that provide connectivity for Advanced driver-assistance systems (ADAS), in-vehicle infotainment (IVI) and other surround-sensor applications. “Our swift response and immediate availability of our MIPI A-PHY v1.0 Verification IP firmly establishes us in the automotive market segment,” affirms Deepak Kumar Tala, managing director of SmartDV, the Proven and Trusted choice for Design and Verification IP. “This achievement is due to our proprietary, automated compiler-based technology that ensures our IP is compliant with standard protocol specifications for new or evolving applications.”

As with all SmartDV fast, highly configurable and reusable plug-and-play Verification IP, users get to market quickly and confidently. The MIPI A-PHY v1.0 Verification IP can be used throughout a coverage-driven chip design verification flow in simulation, emulation, field programmable gate array (FPGA) prototyping. It also features SimXL™, Synthesizable Transactors for accelerating system-level, system-on-chip (SoC) testing on hardware emulators or FPGA prototyping platforms. SimXL allows early software development on an FPGA platform, as well as fast porting of simulation tests to emulators and FPGA platforms.

A configurable bus functional model (BFM), protocol monitor and library of integrated protocol checks come standard with SmartDV’s Verification IP. The IP supports all major verification languages and methodologies, including the open verification methodology (OVM), universal verification methodology (UVM) and SystemC.

Availability and Pricing

The SmartDV MIPI A-PHY v1.0 Verification IP is available now and backed by an experienced R&D team that works individually with each user installation. Advanced configuration and status reporting interfaces are supplied, along with a comprehensive test suite that can be implemented in ASIC, SoC or FPGA designs.

Pricing is available upon request. Fast turnaround customization is available.

Email requests for datasheets or more information should be sent to sales@Smart-DV.com.

About SmartDV

SmartDV™ Technologies is the Proven and Trusted choice for Design and Verification IP with the best customer service from more than 250 experienced ASIC and SoC design and verification engineers. SmartDV offers high-quality standard protocol Design and Verification IP for simulation, emulation, field programmable gate array (FPGA) prototyping, post-silicon validation, formal property verification and RISC-V CPU verification. All of its Design and Verification IP solutions can be rapidly customized to meet specific customer design needs. The result is Proven and Trusted Design and Verification IP used in hundreds of networking, storage, automotive, bus, MIPI and display chip projects throughout the global electronics industry. SmartDV is headquartered in Bangalore, India, with U.S. headquarters in San Jose, Calif.

Connect with SmartDV at:

Website: www.Smart-DV.com

Linkedin: https://www.linkedin.com/company/smartdv-technologies/about/

Twitter: @SmartDV

Leave a Reply

featured blogs
Nov 25, 2020
It constantly amazes me how there are always multiple ways of doing things. The problem is that sometimes it'€™s hard to decide which option is best....
Nov 25, 2020
[From the last episode: We looked at what it takes to generate data that can be used to train machine-learning .] We take a break from learning how IoT technology works for one of our occasional posts on how IoT technology is used. In this case, we look at trucking fleet mana...
Nov 25, 2020
It might seem simple, but database units and accuracy directly relate to the artwork generated, and it is possible to misunderstand the artwork format as it relates to the board setup. Thirty years... [[ Click on the title to access the full blog on the Cadence Community sit...
Nov 23, 2020
Readers of the Samtec blog know we are always talking about next-gen speed. Current channels rates are running at 56 Gbps PAM4. However, system designers are starting to look at 112 Gbps PAM4 data rates. Intuition would say that bleeding edge data rates like 112 Gbps PAM4 onl...

featured video

AI SoC Chats: Protecting Data with Security IP

Sponsored by Synopsys

Understand the threat profiles and security trends for AI SoC applications, including how laws and regulations are changing to protect the private information and data of users. Secure boot, secure debug, and secure communication for neural network engines is critical. Learn how DesignWare Security IP and Hardware Root of Trust can help designers create a secure enclave on the SoC and update software remotely.

Click here for more information about Security IP

featured paper

Top 9 design questions about digital isolators

Sponsored by Texas Instruments

Looking for more information about digital isolators? We’re here to help. Based on TI E2E™ support forum feedback, we compiled a list of the most frequently asked questions about digital isolator design challenges. This article covers questions such as, “What is the logic state of a digital isolator with no input signal?”, and “Can you leave unused channel pins on a digital isolator floating?”

Click here to download the whitepaper

Featured Chalk Talk

Maxim's First Secure Micro with ChipDNA PUF Technology

Sponsored by Mouser Electronics and Maxim Integrated

Most applications today demand security, and that starts with your microcontroller. In order to get a truly secure MCU, you need a root of trust such as a physically unclonable function (PUF). In this episode of Chalk Talk, Amelia Dalton chats with Kris Ardis of Maxim Integrated about how the Maxim MAX32520 MCU with PUF can secure your next design.

Click here for more info about Amphenol RF 5G Wireless Connectors