industry news
Subscribe Now

Silexica’s SLX FPGA 2020.3 Delivers 2x Performance Improvements For FinTech

San Jose, CA – October 5, 2020 – Silexica (silexica.com) has announced the release of SLX FPGA 2020.3 with 2x performance improvements for FinTech designs compared to the previous release, SLX FPGA 2020.2. These enhancements empower financial institutions and exchanges to optimize their designs and decrease time-to-market. Further improvements to the area/performance models and the SLX FPGA optimization engine result in an overall performance increase of 1.24x across all designs, involving almost 100 benchmarks. The release of SLX FPGA 2020.3 further enables developers to convert C/C++ code into an FPGA more easily, faster, and with higher performance.

“In Fintech, next-generation compute acceleration is critical to solve fundamental challenges, such as improved latency and determinism,” said Jordon Inkeles, VP of Product at Silexica. “To enable these compute requirements, financial companies and exchanges are beginning to leverage programmable hardware and high-level synthesis (HLS) design methodology.”

SLX FPGA Enables Developers to Overcome HLS Challenges

Adopting an HLS methodology presents challenges that must be considered and overcome during the design process. SLX FPGA tackles the problems associated with the HLS design flow, including non-synthesizable C/C++ code, non-hardware aware C/C++ code, detecting application parallelism, and determining which pragmas to insert and the pragma attributes to help engineers prepare and optimize their C/C++ application code for HLS.

New features and enhancements to SLX FPGA 2020.3 include:

  • Significant improvements to the area/performance models and optimization engine.
  • The Xilinx® Support Archive (.xsa) file format supported by Xilinx® Vivado HLS 2019.2 can now be imported to SLX.
  • Support has been added for Xilinx® Vivado HLS 2020.1.
  • A number of usability enhancements have been introduced to make visualizations more clear and consistent.

As an active member of the Securities Technology Analysis Center (STAC), Silexica will be presenting at the Global STAC Summit™ on October 19th to discuss important technical challenges in trading and investment. Register here.

Sales Inquiry

Please contact us if you are interested in seeing a live demo or exploring an evaluation of SLX FPGA. 

About Silexica

Silexica provides software development tools allowing technology companies to take innovative IP and intelligent products from concept to deployment. Enabled by metrics-driven software analysis and execution behavior insights, the SLX programming tools accelerate the journey from software to application-specific hardware.

Founded in 2014, Silexica is headquartered in Germany with offices in the US and Japan. It serves innovative companies in the automotive, robotics, wireless communications, aerospace, and financial industries and has received $28M in funding from international investors.

Leave a Reply

featured blogs
Nov 25, 2020
It constantly amazes me how there are always multiple ways of doing things. The problem is that sometimes it'€™s hard to decide which option is best....
Nov 25, 2020
[From the last episode: We looked at what it takes to generate data that can be used to train machine-learning .] We take a break from learning how IoT technology works for one of our occasional posts on how IoT technology is used. In this case, we look at trucking fleet mana...
Nov 25, 2020
It might seem simple, but database units and accuracy directly relate to the artwork generated, and it is possible to misunderstand the artwork format as it relates to the board setup. Thirty years... [[ Click on the title to access the full blog on the Cadence Community sit...
Nov 23, 2020
Readers of the Samtec blog know we are always talking about next-gen speed. Current channels rates are running at 56 Gbps PAM4. However, system designers are starting to look at 112 Gbps PAM4 data rates. Intuition would say that bleeding edge data rates like 112 Gbps PAM4 onl...

featured video

AI SoC Chats: Protecting Data with Security IP

Sponsored by Synopsys

Understand the threat profiles and security trends for AI SoC applications, including how laws and regulations are changing to protect the private information and data of users. Secure boot, secure debug, and secure communication for neural network engines is critical. Learn how DesignWare Security IP and Hardware Root of Trust can help designers create a secure enclave on the SoC and update software remotely.

Click here for more information about Security IP

featured paper

Learn how designing small is easier than you think

Sponsored by Texas Instruments

Designing with small-package ICs is easier than you think. Find out how our collection of industry's smallest signal-chain products can help you optimize board space without sacrificing features, cost, simplicity, or reliability in your system.

Click here to download the whitepaper

Featured Chalk Talk

Accelerate HD Ultra-Dense Multi-Row Mezzanine Strips

Sponsored by Mouser Electronics and Samtec

Embedded applications are putting huge new demands on small connectors. Size, weight, and power constraints are combining with new signal integrity challenges due to high-speed interfaces and high-density connections, putting a crunch on connectors for embedded design. In this episode of Chalk Talk, Amelia Dalton chats with Matthew Burns of Samtec about the new generation of high-performance connectors for embedded design.

More information about Samtec AcceleRate® HD Ultra-Dense Mezzanine Strips: