[March 14, 2019] – At the OCP Summit 2019, the Power Stamp Alliance (PSA), which is creating collaborative solutions for 48V-to-low-voltage on-board DC-DC power converters, today announced a new reference design board for processors based on the next-generation 10 nm Intel® CPU microarchitecture, code-named “Ice Lake” by Intel®. Engineers designing high-performance computers and servers being used in large data centers, which are increasingly using 48-volt rack-level power distribution systems, can now match the performance and energy efficiency of these new processors with a flexible and efficient point-of-load power solution backed by a multi-vendor ecosystem.
PSA 48V direct conversion DC-DC modules – or ‘power stamps’ – primarily target advanced IT equipment and large data processing installations, many of which follow the principles of the Open Compute Project (OCP).
The new reference design board for Intel’s upcoming first volume 10nm processor will enable design engineers to evaluate the power stamp concept and specific point-of-load stamps from dc-dc vendors. It can help to accelerate the project development cycle for new server designs and other equipment using the latest Intel® processors in a 48 V rack environment. This latest reference design board extends the Power Stamp Alliance’s portfolio of reference design boards, which include a board suitable for the Intel® VR13 (Intel® code-named Skylake) processor architecture and a board for ASIC devices. The Power Stamp Alliance has a roadmap for future reference design boards for processor architectures used in high-performance computing.
Background Information
By creating and sharing a specification for a standard product footprint and functions, the Power Stamp Alliance has created a multi-vendor ecosystem to assure practical levels of alternate source capability to server and storage system manufacturers, while encouraging a competitive supply chain through differentiation in topology, circuitry, and performance from multiple, independent manufacturers. Formally launched at the Open Compute Project (OCP) Summit in 2018 with the publication of specifications, drawings and pin-out descriptions for main and satellite power stamps, the Alliance has since also published a new Orcad Library and Allegro Footprint Package (Macro) to its website to enable designers to embed Power Stamps into their own schematic, along with the linked Allegro reference footprint for proper layout. Most recently, the Alliance announced the industry’s first graphical user interface (GUI) that developers can use with products from any member company, and a new reference design board for high-current ASIC and/or FPGA chipsets.
PSA reference design boards, power stamps and the GUI are available from PSA member representatives, who can be contacted via the Power Stamp Alliance website http://www.powerstamp.org/contact/.
The Power Stamp Alliance will be represented at the OCP Summit 2019 by its Founding Members, Artesyn Embedded Technologies, Bel Power Solutions, Flex, and STMicroelectronics.
About the Power Stamp Alliance
The Power Stamp Alliance has been formed to define a standard product footprint and functions that provide a multiple sourced, standard modular board-mounted solution for power conversion for 48Vin to low-voltage, high-current DC-DC applications. These 48V single-stage, direct-conversion DC-DC modules – or ‘power stamps’ – primarily target devices being used in large data centers (e.g. high-performance computers, ASICs, and FPGAs), many of which follow the principles of the Open Compute Project (OCP). The Founding Members of the Power Stamp Alliance are Artesyn Embedded Technologies, Bel Power Solutions, Flex, and STMicroelectronics.
