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Lattice Announces New Low Power FPGA Platform

Lattice Nexus Platform Delivers Solution, Architecture and Circuit-Level Innovations to Enable Low Power Edge Applications
December 11, 2019

HILLSBORO, OR – December 10, 2019 – Lattice Semiconductor Corporation (NASDAQ: LSCC), the low power programmable leader, today announced its new low power FPGA platform, Lattice Nexus™. The platform is architected to deliver power-efficient performance that will benefit developers of a wide range of applications, including AI for IoT, video, hardware security, embedded vision, 5G infrastructure and industrial/automotive automation. Lattice Nexus is built with innovations at every level of design, from solutions, to architecture, to circuit, and delivers higher system … Read More → "Lattice Announces New Low Power FPGA Platform"

Lattice Accelerates FPGA Design with New Lattice Radiant 2.0 Design Software

Latest Version Supports New Lattice CrossLink-NX FPGAs
December 11, 2019

HILLSBORO, OR – December 10, 2019 – Lattice Semiconductor Corporation (NASDAQ: LSCC), the low power programmable leader, today announced the availability of the latest version of its popular software design tool for FPGAs, Lattice Radiant™ 2.0. In addition to adding support for higher density devices like the new CrossLink-NX™ FPGA family, the updated design tool also offers new features that make it faster and easier than ever to develop Lattice FPGA-based designs.

… Read More → "Lattice Accelerates FPGA Design with New Lattice Radiant 2.0 Design Software"

NSITEXE Selects SmartDV TileLink Verification IP for RISC-V Based Applications

Smart TileLink VIP to be Used to Ensure Complete Verification of High-Efficiency, High-Quality Semiconductor IP
December 11, 2019

SAN JOSE, CALIF –– December 10, 2019 –– SmartDV™ Technologies, the Proven and Trusted choice for Verification Intellectual Property (VIP), today announced NSITEXE licensed its TileLink VIP to ensure complete verification of its high-efficiency and high-quality semiconductor IP adaptable to various applications using the RISC-V architecture.

NSITEXE selected SmartDV because it is the only VIP solutions provider to offer a smart way to verify the TileLink fabric and reduce verification time. SmartDV’s VIP verifies … Read More → "NSITEXE Selects SmartDV TileLink Verification IP for RISC-V Based Applications"

Breker Verification Systems Launches Unique RISC-V TrekApp for Automated, High-Coverage System Integration Test Suite Synthesis

Developed with SiFive to Address RISC-V System Integration Validation; Generates High-Impact SoC Verification Test Suite with Minimal Manual Effort
December 11, 2019

SAN JOSE, CALIF. –– December 10, 2019 –– Breker Verification Systems, the leading provider of Test Suite Synthesis tools based on the Portable Stimulus Standard (PSS), today introduced its RISC-V TrekApp, a complete, automated test content generator for RISC-V system integration testing. 

RISC-V TrekApp, the first solution to address the entire RISC-V system-on-chip (SoC) system integration problem, … Read More → "Breker Verification Systems Launches Unique RISC-V TrekApp for Automated, High-Coverage System Integration Test Suite Synthesis"

More than meets the eye: Bosch enables the next generation of smartglasses

Innovative Light Drive system for smartglasses creates the first transparent, lightweight, and stylish user experience
December 11, 2019
  • World’s first all-day transparency smartglasses solution
  • Smallest Light Drive on the market: 30 percent less depth
  • Highly efficient, lightweight system, weighing less than 10 grams
  • Delivers high quality, bright images, even in direct sunlight
  • Turnkey Light Drive display solution, for rapid integration
  • Visit Bosch at CES®: LVCC, central hall, booth 12401

At CES® in Las Vegas, Nevada, Bosch Sensortec launches an innovative optical Light Drive system for smartglasses. The … Read More → "More than meets the eye: Bosch enables the next generation of smartglasses"

ELDORADO Selects AdaCore’s QGen for Critical Medical Applications

Model-based engineering toolsuite brings high reliability to medical device software
December 11, 2019

NEW YORK and PARIS and Campinas, Brazil, December 10, 2019 – AdaCore today announced that The ELDORADO Research Institute of Brazil (ELDORADO) has selected the QGen model-based code generation and verification toolsuite to support research and development of safety-critical medical device software. These applications demand high reliability and currently include a cardiac pacemaker as well as perfusion systems for cardiac surgery and chemotherapy.

ELDORADO develops products for the medical industry, which, like most sectors of the globalized economy, is under great pressure to be innovative, competitive and profitable. Based on the underlying life science, medical device development uses … Read More → "ELDORADO Selects AdaCore’s QGen for Critical Medical Applications"

OpenHW Group announces CORE-V Chassis SoC project and issues industry call for participation

CORE-V Chassis SoC to include CORE-V family of open-source RISC-V cores including a Linux capable 64-bit processor coupled with a 32-bit coprocessor
December 10, 2019

San Jose, California – RISC-V Summit, December 10 2019: With the CORE-V Chassis project, the recently formed OpenHW Group aims to tape out a heterogeneous multi-core processor evaluation SoC, capable of running the Linux operating system during the 2nd half of 2020. The CORE-V Chassis will see a CV64A 64-bit core running alongside a CV32E 32-bit coprocessor core.

Based on the proven NXP iMX platform, the resulting CORE-V Chassis evaluation SoC will also feature 3D and 2D GPUs, MIPI-DSI and CSI display and camera I/O, hardware security blocks, PCIe connectivity, a GigE MAC, USB 2.0 interfaces, support for (LP) … Read More → "OpenHW Group announces CORE-V Chassis SoC project and issues industry call for participation"

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