industry news
Subscribe Now

NSITEXE Selects SmartDV TileLink Verification IP for RISC-V Based Applications

Smart TileLink VIP to be Used to Ensure Complete Verification of High-Efficiency, High-Quality Semiconductor IP

SAN JOSE, CALIF –– December 10, 2019 –– SmartDV™ Technologies, the Proven and Trusted choice for Verification Intellectual Property (VIP), today announced NSITEXE licensed its TileLink VIP to ensure complete verification of its high-efficiency and high-quality semiconductor IP adaptable to various applications using the RISC-V architecture.

NSITEXE selected SmartDV because it is the only VIP solutions provider to offer a smart way to verify the TileLink fabric and reduce verification time. SmartDV’s VIP verifies the TileLink chip-scale interconnect standard, an open-source, high-performance and scalable cache-coherent fabric for RISC-V based or alternative architecture system-on-chip (SoC) designs.

According to Hideki Sugimoto, chief technology officer (CTO) at NSITEXE, Choosing SmartDV’s TileLink VIP was a smart decision for its power-efficient data flow processor (DFP) IP used in in-vehicle, industrial applications, and other market segments. “It accelerated TileLink implementation and verification through faster testbench development.”

“NSITEXE’s mission to contribute to the evolution of next-generation semiconductor technology through its semiconductor IP products neatly aligns with our mission and goals,” remarks Deepak Kumar Tala, SmartDV’s managing director. “We pride ourselves on evolving next-generation SoC designs with our sizable portfolio of standard and custom protocol VIP fully compliant with standard protocol specifications. Users like NSITEXE can verify and debug their designs quickly, easily and more effectively.”

SmartDV will exhibit at the RISC-V Summit today (Tuesday, December 10) from 11:30 a.m. until 7 p.m. and Wednesday, December 11, from 11:30 a.m. until 4 p.m. at the San Jose Convention Center, San Jose, Calif. It will highlight the TileLink VIP and its Verilator VIP, and demonstration its Smart ViPDebug™, a visual protocol debugger that reduces debug time. Attendees can schedule demos or meetings at demo@smart-dv.com

About SmartDV

SmartDV™ Technologies is the Proven and Trusted choice for Verification and Design IP with the best customer service from more than 250 experienced ASIC and SoC design and verification engineers. Its high-quality standard or custom protocol Design and Verification IP supports simulation, emulation, field programmable gate array (FPGA) prototyping, post-silicon validation, formal property verification, RISC-V verification services. The result is Proven and Trusted Design and Verification IP used in hundreds of networking, storage, automotive, bus, MIPI and display chip projects throughout the global electronics industry. SmartDV is headquartered in Bangalore, India, with U.S. headquarters in San Jose, Calif. Visit SmartDV to learn more. 

Connect with SmartDV at:

Linkedin: https://www.linkedin.com/company/smartdv-technologies/about/ 

Twitter: @SmartDV 

Leave a Reply

featured blogs
Apr 16, 2024
In today's semiconductor era, every minute, you always look for the opportunity to enhance your skills and learning growth and want to keep up to date with the technology. This could mean you would also like to get hold of the small concepts behind the complex chip desig...
Apr 11, 2024
See how Achronix used our physical verification tools to accelerate the SoC design and verification flow, boosting chip design productivity w/ cloud-based EDA.The post Achronix Achieves 5X Faster Physical Verification for Full SoC Within Budget with Synopsys Cloud appeared ...
Mar 30, 2024
Join me on a brief stream-of-consciousness tour to see what it's like to live inside (what I laughingly call) my mind...

featured video

How MediaTek Optimizes SI Design with Cadence Optimality Explorer and Clarity 3D Solver

Sponsored by Cadence Design Systems

In the era of 5G/6G communication, signal integrity (SI) design considerations are important in high-speed interface design. MediaTek’s design process usually relies on human intuition, but with Cadence’s Optimality Intelligent System Explorer and Clarity 3D Solver, they’ve increased design productivity by 75X. The Optimality Explorer’s AI technology not only improves productivity, but also provides helpful insights and answers.

Learn how MediaTek uses Cadence tools in SI design

featured chalk talk

FlyOver® Technology: Twinax FlyOver® System for Next Gen Speeds -- Samtec and Mouser
Sponsored by Mouser Electronics and Samtec
In this episode of Chalk Talk, Amelia Dalton and Matthew Burns from Samtec investigate the challenges of routing high speed data over lossy PCBs. They also discuss the benefits that Samtec’s Flyover® cable assembly systems bring to data center and embedded designs and how Samtec is furthering innovation with their high speed interconnect solutions. 
Apr 15, 2024
236 views