Highlights:
• New solution accelerates IP-to-SoC-level verification for complex memory controllers, PHYs and devices for LPDDR5x, DDR5, HBM3 and GDDR6 protocols
• Up to 10X increase in verification throughput enables total IP-to-SoC-level verification of advanced designs with multiple DDR interfaces
SAN JOSE, Calif., January 20, 2022— Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced a new DRAM verification solution, allowing customers to test and optimize system-on-chip (SoC) designs for data center, consumer, mobile and automotive applications. Using the full DRAM verification solution, which delivers up to 10X increased verification throughput, customers can quickly and effectively perform … Read More → "Cadence Announces Full DRAM Verification Solution for Automotive, Data Center, and Mobile Applications"