SystemVerilog Analyzer, Static Elaborator Serve as Front End to New Synthesis Software for Asynchronous Chip Design

ALAMEDA, Calif.–(BUSINESS WIRE)–Tiempo, provider of breakthrough, ultra low-power asynchronous intellectual property (IP) for embedded applications, has chosen Verific Design Automation, a de facto industry standard, as the front end for its software products.

Tiempo licenses Verific’s SystemVerilog analyzer and static elaborator to serve as the front end to its Asynchronous Circuit Compiler (ACC), synthesis software that generates asynchronous and delay-insensitive circuits from a model written in SystemVerilog.

“Verific’s software … Read More → "Tiempo Chooses Verific Design Automation’s SystemVerilog Front End"

MILPITAS, SUNNYVALE and FREMONT, Calif., Oct. 27 /PRNewswire/ — Open-Silicon, Inc., MIPS Technologies, Inc. (NASDAQ:MIPS) , and Virage Logic (NASDAQ:VIRL) today announced the co-development of test chips showcasing the companies’ industry-leading technologies for building high-performance processor-based systems. The companies achieved successful 65 nanometer (nm) silicon testing of a processor test chip at 1.1GHz, making it one of the fastest processors built in a 65nm ASIC. Also, work has begun on a follow-on 40nm device targeting frequencies in excess of 2.5GHz and providing over 5000 DMIPS of performance. Both efforts utilize Open-Silicon’s CoreMAX(TM) technology as well as the superscalar MIPS32& … Read More → "Open-Silicon, MIPS Technologies, and Virage Logic Achieve High Performance ASIC Processor Design 65nm Silicon Runs 1.1GHz Today; 40nm Target to Exceed 2.5GHz"

SRS Releases Optimized SRS TruVolume Libraries for MIPS32 4KEc and 24KEc Core Licensees

SANTA ANA, Calif., Oct. 27 /PRNewswire-FirstCall/ — SRS Labs (NASDAQ: SRSL) , the industry leader in surround sound, audio, and voice technologies, announced today the availability of highly optimized SRS TruVolume(TM) libraries for Digital TV System-on-Chips (SoCs) based on processor cores from MIPS® Technologies. DTV OEMs can now enable SRS’ audio leveling technology, TruVolume, on TV and DTV SoCs based upon MIPS32® 24KEc(TM) and 4KEc® cores. With a pre-ported and optimized library for TruVolume, MIPS® licensees and SRS TruVolume licensees … Read More → "SRS TruVolume Now Available for MIPS Cores, Delivering Fast, Efficient Deployment for DTV SoCs"

Free Example Projects at www.cypress.com Allow Embedded Developers to Implement Designs More Quickly with Easily-Replicated, Robust IP Elements

SAN JOSE, Calif.–(BUSINESS WIRE)–Cypress Semiconductor Corp. (NYSE:CY) today announced the availability of over 30 intellectual property (IP) elements for its new PSoC® 3 programmable system-on-chip architectures. The embedded design resources include example projects, application notes and solution overviews, all of which enable engineers to quickly implement designs using the unique new PSoC Creator™ integrated development environment (IDE). The solution IP Elements are available for free at www.cypress.com/go/psoc3.

… Read More → "Cypress Provides Solutions IP for New PSoC® 3 Devices and Revolutionary PSoC Creator™ IDE"

What: The application note describes the Agilent PSG Option 521, and its applications in high-power output signals. With Option 521 installed, the PSG simplifies the testing of high-power amplifiers, overcomes losses within automated test equipment (ATE) systems, and addresses the attenuation of signals within long cable runs. Additional benefits described are reduced cost, size and weight for test configurations/systems.

When: Available now

Where: To download the application note: http://cp.literature.agilent.com/litweb/pdf/5990-4695EN.pdf

Additional
Information: www.agilent.com/find/AD

WINSTON-SALEM, N.C. – September 27, 2009 – Triad Semiconductor Inc., the industry’s leading supplier of via-configurable mixed-signal ASICs, will demonstrate its silicon-proven via-configurable array (VCA) technology for analog, digital and mixed-signal design at the 7th International System-on-chip (SoC) Conference and Workshops in Newport Beach, California, on November 4th, 2009. The company’s CTO, Jim Kemerling, also will present on “Via-configurable, Mixed-signal Embedded ASICs Using the ARM Cortex-M0 Microcontroller.”

What:
Exhibiting: The Triad Mocha™ family of ARM Powered® VCAs, which combine the ARM® Cortex™-M0 processor with … Read More → "Triad Semiconductor to Exhibit at International SoC Conference and Present on Via-configurable, Mixed-signal Embedded ASICS Using the ARM Cortex-M0 Microcontroller"

WIN Semiconductors today announced the availability of a new MMIC tool bar personality for ten Advanced Design System (ADS) process design kits (PDKs) for its popular Enhancement/Depletion-Mode PHEMT and HBT process technologies. The new add-on WIN PDKs, developed for use with current and future releases of Agilent Technologies’ ADS 2009, enable high-frequency RF and microwave designers to create compact integrated circuits comprised of power amplifiers, switches, low-noise amplifiers, mixers, and logic circuitry. The add-on PDKs are available now from WIN Semiconductors.

“These add-on kits will significantly improve the design experience for our mutual customers working on … Read More → "WIN Semiconductors Announces New MMIC Tool Bar Personality for Agilent Technologies’ ADS Process Design Kits"

WILSONVILLE, Ore., October 22, 2009 – Mentor Graphics Corporation (NASDAQ: MENT) today announced that Taiwan Semiconductor Manufacturing Company (TSMC) selected the Calibre® physical verification platform for its Integrated Sign-Off (ISO) Flow, which integrates tools, setup files, and flow management utilities to provide mutual customers with an automated design solution for implementing their chips in TSMC technologies. The new flow is now available for 65nm designs with planned extensions into other process technology nodes.

According to ST Juang, senior director of Design Infrastructure Marketing at TSMC,
“Integrated Sign-Off Flow leverages our close partnership with eco-system partners to … Read More → "TSMC Selects Calibre Physical Verification Platform for Integrated Sign-off Flow"

TestShell Test Automation platform accelerates test creation with multiple new features

22 October 2009, Tel Aviv, Israel; QualiSystems Ltd announced today the release to market of TestShell 4.1, its latest and most advanced version of the award-winning automated test solutions for hardware, devices and embedded systems (http://tinyurl.com/ylkx464). TestShell 4.1 is packed with groundbreaking new features, providing TestShell users with greater usability and flexibility than ever before.

TestShell Test Authoring Applications in particular enjoy a great boost in versatility and capabilities. Session Management allows greater control and tracking of tests, steps and functions; Enhanced … Read More → "QualiSystems releases feature-rich TestShell 4.1"

Deadlines Begin on October 26, 2009

Design Automation Conference 2010
LOUISVILLE, Colo.–(BUSINESS WIRE)–The 47th Design Automation Conference (DAC), the premier conference devoted to electronic design and design automation (EDA), has opened the first Call for Contributions to the technical program. The 47th DAC will be held at the Anaheim Convention Center, in Anaheim, California from June 13-18, 2010. IC designers, application engineers, design flow developers, vendor-customer teams and students are invited to submit proposals for eight different areas of the technical program enumerated below. DAC is also accepting proposals for workshops and co-located events.

Special … Read More → "47th Design Automation Conference Announces Calls for Submissions to Technical Program"