SAN JOSE, CA–(Marketwire – May 29, 2012) – “As the performance of the processors used in today’s consumer electronics devices improves, so does their need for higher-bandwidth memory. The DFI interface standard was developed to give SoC designers a way to easily incorporate high-performance memory into their SoCs,” said Marc Greenberg, director of marketing, SoC Realization, Cadence. “Through our close working relationship with the DFI Group, we are able to offer our customers design and verification IP that supports the latest version of this popular interface standard.”Cadence Design Systems, Inc. (NASDAQ: Read More → "Cadence Announces Updated Design and Verification IP for DDR PHY Interface"

OXFORD, United Kingdom, May 22, 2012 – Imperas today announced that its Open Virtual Platforms (OVP) OVPsim simulator and OVP Fast Processor Models have been integrated with NEC’s CyberWorkBench (CWB) SystemC cycle-accurate hardware models. OVP\’s position as the de facto source of instruction accurate processor core models provides additional value to CyberWorkBench’s complete C/SystemC SoC design flow including ANSI-C/SystemC synthesis, hardware-software (HW/SW) co-verification and C-based formal verification.

CyberWorkBench is a C-based electronic circuit design platform developed by NEC over the course of twenty years. CyberWorkBench … Read More → "NECs CyberWorkBench and Imperas OVP Fast Processor Models Integrated to Expand Hardware-Software Co-Verification Capabilities"

WILSONVILLE, Ore., May 29, 2012—Mentor Graphics Corporation (NASDAQ: MENT) today announced that GLOBALFOUNDRIES will use the SmartFill facilities of the Calibre® YieldEnhancer product to enable advanced fill techniques for 20nm manufacturing processes. The multi-layer fill analysis and cell-based fill generation capabilities of the SmartFill system help designers deal with complex fill interactions at advanced nodes with minimal impact on circuit performance. Moreover, Calibre SmartFill delivers greatly reduced post-fill GDS database size and faster runtimes compared to traditional dummy fill. Used with the design kit provided by GLOBALFOUNDRIES, Calibre SmartFill allows designers to meet IC fill constraints in a single … Read More → "Mentor Graphics and GLOBALFOUNDRIES Collaborate on 20nm Fill Solutions Based on Calibre SmartFill"

GRENOBLE, France – May 24, 2012. The ANR (French National Research Agency) and the CEA (French Atomic and Renewable Energy Commission) signed an agreement forming the Grenoble Institute of Technological Research (IRT): NanoElec Program.

Based on Grenoble’s pioneering ecosystem, the IRT partners aim to conduct world-class R&D, and to share their research with all industrial sectors, especially small, medium and intermediate sized enterprises, as well as to provide training in the necessary skills in these areas, specifically micro and nano-electronics.

The technological R&D activities will focus on 3D IC integration and integrated silicon-photonics … Read More → "Mentor Graphics, STMicroelectronics and CEA-Leti join to launch the technological R&D programs of the NanoElec IRT"

SANTA CLARA, Calif., May 24, 2012 – Agilent Technologies Inc. (NYSE: A) today introduced the oscilloscope industry’s first eye-diagram mask testing capability for the differential Controller Area Network serial bus. The CAN serial bus is used extensively for control and sensor monitoring in automotive applications as well as a broad range of industrial and medical equipment applications.

For years, oscilloscopes have been the primary measurement tools used to verify the signal integrity of the … Read More → "Agilent Technologies Introduces CAN Eye-Diagram Mask Testing on InfiniiVision X-Series Oscilloscopes"