SANTA CLARA, CALIF. –– June 3, 2013 –– OneSpin Solutions™ (www.onespin-solutions.com), provider of innovative formal assertion-based verification (ABV) and formal equivalence checking solutions, invites attendees of the 50th Design Automation Conference (www.dac.com) to become Beta users of its new Cloud Computing System.

Austin, TX – June 3, 2013 – Vayavya Labs Inc. (Santa Clara, CA), a subsidiary of Vayavya Labs Pvt. Ltd (India) today announced SOCX-Verifier™, the EDA industry’s first software-driven verification tool that automatically generates verification test software and relevant test-bench components from a system-level scenario specification. With SOCX-Verifier, SoC designers can now bridge and thus greatly accelerate the arduous hardware-software co-design process.

Bridging the hardware-software design flow

Traditionally, SoC hardware and software teams have worked in silos with each team being focused on their specific concerns or objectives. As a result, the efforts in writing test … Read More → "Vayava Labs Introduces First Automated Software-Driven Verification Tool"

WILSONVILLE, Ore., May 31, 2013—Mentor Graphics Corp. (NASDAQ: MENT today announced that Calibre® nmDRC™ and Calibre nmLVS rule decks for Samsung’s 14nm IC manufacturing processes have been significantly improved since first release. For example, the joint efforts have resulted in a 50% better performance over the previous release for the Calibre nmDRC design kit. The revised decks provide rapid turnaround and also reduce customers’ datacenter costs by reducing compute platform memory requirements. While cycle time is important for every process node, with the significant increase in design sizes at 14nm, continuous performance optimization of verification run times is especially … Read More → "Mentor Graphics and Samsung Optimize 14nm Process Design Kits"

DESIGN AUTOMATION CONFERENCE, Austin, Texas – June 3, 2013– Ausdia, the leading developer of timing constraints verification and management solutions that complement timing signoff for complex system-on-chip (SoC) designs, introduced an add-on product for its comprehensive Timevision timing constraints development, verification and management solution at DAC 2013. Timevision-CDC checks the safety of asynchronous clock domain crossings while simultaneously leveraging and verifying the SDC (Synopsys design constraint) file that specifies the asynchronous relationships.

SoC designs in custom silicon are getting progressively more complicated and harder to design and verify, as well … Read More → "Ausdia Introduces Timing Constraints Generation and Validation Add-on to Timevision at DAC 2013"