Austin, TX – June 3, 2013 – Vayavya Labs Inc. (Santa Clara, CA), a subsidiary of Vayavya Labs Pvt. Ltd (India) today announced SOCX-Verifier™, the EDA industry’s first software-driven verification tool that automatically generates verification test software and relevant test-bench components from a system-level scenario specification. With SOCX-Verifier, SoC designers can now bridge and thus greatly accelerate the arduous hardware-software co-design process.
Bridging the hardware-software design flow
Traditionally, SoC hardware and software teams have worked in silos with each team being focused on their specific concerns or objectives. As a result, the efforts in writing test software or drivers during system-level verification rarely get re-used by the software team. While there are flows that are based on virtual platforms and emulation platforms, there is still a huge amount of effort and cost involved in developing embedded software for SoCs. SOCX-Verifier closes this gap by providing all the necessary building blocks for driver-model generation, scenario specification and virtualizing test-bench interaction to give verification teams a speedier closure and effective system-level verification. Further this also enables the software developers to deliver production ready software drivers at a 10x efficiency level. In other words, SOCX-Verifier replaces the current “how to test” problem with the more specific “what to test” capability.
How does SOCX-Verifier work?
Current SoC development requires designers to approach the SoC as a combination of hardware and software to be verified together. Software-driven verification methodology is a step in that direction which harnesses the embedded processor core’s power to verify the SoC from “Inside-Out.”
Such a methodology presents a challenge of what software to run and how to create system-level scenarios for effective verification. SOCX-Verifier addresses these challenges in methodology and productivity terms by replacing the “how to test?” with “what to test?”
SOCX-Verifier provides verification designers with the required infrastructure and building blocks for driver-model generation, scenario specification and virtualizing test-bench interaction for a speedier closure and effective system-level verification. SOCX-Verifier consists of two main components: SOCX-Specifier and SOCX-Virtualizer.
SOCX-Specifier provides the canvas for capturing the scenario specifications and generates C test cases from this specification. The C test cases execute on the embedded processor core(s) in the SoC and access the design-under-test (DUT) components (design IP blocks) and the test-bench.
The benefit? SOCX-Specifier takes away the verification engineer’s need to know the nitty-gritty details of the verification environment (including OS) APIs or driver model details while specifying scenarios.
SOCX-Virtualizer virtualizes access to the DUT components as well as the test-bench across various verification platforms. It achieves this by means of a “verification aware” lightweight operating system (OS) and the DDGen tool which automatically generates device drivers for the DUT components. This abstraction proves invaluable during the scenario specification since verification engineers can now refer to test-bench components in the scenario specification. This is similar to their ability to refer to design IP blocks and not worry about the mechanisms of test-bench-DUT interaction in the creation of scenarios.
The SOCX-Verifier flow is depicted below. SOCX-Verifier can be deployed on any test platform with minimum effort. SOCX-Verifier setup involves creation of the device programming specification (DPS) of the IP blocks of the DUT. SOCX-Virtualizer translates the DPS specification of an IP into its device drivers, compatible with Verification-OS. The verification team then specifies the system-level in the scenario specification using the SOCX-Specifier.
Anindya Saha, associate VP, VLSI, at Saankhya Labs (Bangalore, India), said, “Our SDR based SoCs have a high level of increased functionality. Hence, maintaining a high quality verification with shrinking design cycle times is very important for us. The SoCX-Verifier tool from Vayavya Labs helped us to meet this challenge by effectively improving the verification productivity while adhering to all the quality metrics. We have been impressed with the tool’s promise to address our specific verification needs of generating both for C and assembly based tests while allowing us to span the entire gamut of complex scenarios.”
RK, Patil, founder and CEO of Vayavya said, “System-level verification brings out an interesting facet of SoC design, of visualizing the SoC as a combination of hardware and software to be verified together. Use of our software-driven verification methodology is a step in that direction because it harnesses the embedded core’s power to verify the SoC from ‘Inside-Out.’ SoCX-Verifier is built ground-up and is based on the proven technology of software driver automation.”
Availability and Pricing
SOCX-Verifier will be available by mid September 2013. The SOCX-Verifier package, (which includes SOCX-Specifier and SOCX-Virtualizer) is available as a bundled license with the flexibility of a yearly or SoC designs-based licensing model. For more sale information, please email email@example.com or visit http://www.vayavyalabs.com.
Vayavya Labs Inc., is a subsidiary of Vayavya Labs Pvt. Ltd., which is a privately held and Indian Angel Network (IAN) venture funded ESL (Electronic System Level) design tools company. The company re-defines the hardware-software co-design methodology to drive down the TIME, EFFORT and COSTS involved in SoC/ASIC roll-out. Vayavya Labs delivers a high level formal set of design specifications and automation tools that help in bridging the Hardware-Software design flows. Founded in 2006, Vayavya Labs serves the global SoC and Embedded system design firms with its two development centers in India and sales offices in Japan and the USA. For more details about the company and its products visit http://www.vayavyalabs.com/