News – Page 1774 – EEJournal

DFI Group Releases Version 3.1 of Its High-Speed Memory Controller and PHY Interface Specification

May 29, 2012

SAN JOSE, CA–(Marketwire – May 29, 2012) – The DDR PHY Interface (DFI) Group today released the DFI 3.1 specification, the latest version of the pervasive industry specification that defines an interface protocol between DDR memory controllers and PHYs. The specification enables the development of systems-on-chip (SoCs) that support the DDR3 and DDR4 memory standards. Version 3.1 adds support for the LPDDR3 mobile memory standard for smartphones and tablets, as well as enhancements to the low-power interface and training features. The … Read More → "DFI Group Releases Version 3.1 of Its High-Speed Memory Controller and PHY Interface Specification"

Xtendwave selects EnSilica’s eSi-3200 processor for the receiver IC implementing NIST’s next-generation WWVB atomic timekeeping signal

May 29, 2012

Wokingham, UK – 29^th May 2012. EnSilica, a leading independent provider of IC design services and system solutions, has announced that Xtendwave has licensed its high-performance eSi-3200 32-bit processor core to power Everset™, Xtendwave’s time code receiver solution for the next-generation WWVB atomic timekeeping signal. The new signal, broadcast by NIST (the National Institute of Standards and Technology), a US Government agency, will represent the official time of the USA and includes the implementation of daylight saving time and leap seconds.

Xtendwave, a fabless semiconductor company focused on the development of physical-layer communication technologies is developing … Read More → "Xtendwave selects EnSilica’s eSi-3200 processor for the receiver IC implementing NIST’s next-generation WWVB atomic timekeeping signal"

Renesas Electronics Europe releases free VDE certified self-test MCU routines for IEC60730/60335 safety compliance

May 29, 2012

Dusseldorf, May 29, 2012 – Renesas Electronics Europe today announced that it has received VDE certification for its IEC60335-compliant self-test software for the RX200 family of microcontrollers. The latest self-test CPU software routines developed for the RX200 family are fully compliant with IEC60730-1 regulations and have now been certified by VDE (the German Association for Electrical, Electronic & Information Technologies). VDE is widely recognized for its work on safety standards and approvals.

In addition to the on-chip hardware safety features, the self-test CPU software makes … Read More → "Renesas Electronics Europe releases free VDE certified self-test MCU routines for IEC60730/60335 safety compliance"

Flexras Technologies Announces Breakthrough Automatic Partitioning Tool that Boosts FPGA-Based Prototyping Performance by 10X

May 29, 2012

SAN FRANCISCO, CA– Design Automation Conference (DAC) – May 29, 2012 – Flexras Technologies, an EDA company specializing in partitioning for FPGA-based prototyping, today announced Wasga Compiler, a software tool that boosts multi-FPGA design performance. Wasga Compiler is unique and is the first timing-driven, multi-FPGA partitioning software for ASIC and SoC prototyping. It typically delivers a 10X clock frequency increase, runs blazingly fast, handles multi-billion ASIC gates equivalents designs, and maps them to any Altera or Xilinx board, whether it’s off-the-shelf or custom.

Cadence Announces Updated Design and Verification IP for DDR PHY Interface

May 29, 2012

SAN JOSE, CA–(Marketwire – May 29, 2012) – “As the performance of the processors used in today’s consumer electronics devices improves, so does their need for higher-bandwidth memory. The DFI interface standard was developed to give SoC designers a way to easily incorporate high-performance memory into their SoCs,” said Marc Greenberg, director of marketing, SoC Realization, Cadence. “Through our close working relationship with the DFI Group, we are able to offer our customers design and verification IP that supports the latest version of this popular interface standard.”Cadence Design Systems, Inc. (NASDAQ: Read More → "Cadence Announces Updated Design and Verification IP for DDR PHY Interface"

Test System TTsuite Expanded for all MOST® Speed Grades and Physical Layers

May 29, 2012

Munich (Germany) May 29, 2012 – Test specialist RUETZ SYSTEM SOLUTIONS extends its test system TTsuite to all available speed grades and physical layers of the networking standard MOST (Media Oriented Systems Transport) for in-car data transmission. Thus the qualified system integrator for automotive data communication now provides the optimized test system for speed grades of 25, 50 and 150 Mbit/s. The supported physical layers for MOST include POF (plastic optical fiber) and electrical physical layers: coax and shielded or unshielded twisted pair (STP/UTP) copper wires. “With the enhanced and optimized TTsuite, all test cases that have been automated once with TTsuite … Read More → "Test System TTsuite Expanded for all MOST® Speed Grades and Physical Layers"

Standardization Group for Embedded Technologies (SGET) Inaugurated

May 29, 2012

Munich, Germany, 29 May 2012 * * * A group of embedded computing manufacturers have formed a registered association to drive standardization of embedded computing technologies called The Standardization Group for Embedded Technologies (SGET) e.V. The proclaimed aim of the association is to speed up the development of new standards for embedded hardware and software. 23 companies signed up to support the founding principles during the inaugural meeting, among them Advantech, congatec, Data Modul, Kontron, MSC and Seco.

“While there are many board manufacturers among the founding members, SGET also has a clear focus on tackling related issues such as software,” points … Read More → "Standardization Group for Embedded Technologies (SGET) Inaugurated"

NECs CyberWorkBench and Imperas OVP Fast Processor Models Integrated to Expand Hardware-Software Co-Verification Capabilities

May 29, 2012

OXFORD, United Kingdom, May 22, 2012 – Imperas today announced that its Open Virtual Platforms (OVP) OVPsim simulator and OVP Fast Processor Models have been integrated with NEC’s CyberWorkBench (CWB) SystemC cycle-accurate hardware models. OVP\’s position as the de facto source of instruction accurate processor core models provides additional value to CyberWorkBench’s complete C/SystemC SoC design flow including ANSI-C/SystemC synthesis, hardware-software (HW/SW) co-verification and C-based formal verification.

CyberWorkBench is a C-based electronic circuit design platform developed by NEC over the course of twenty years. CyberWorkBench … Read More → "NECs CyberWorkBench and Imperas OVP Fast Processor Models Integrated to Expand Hardware-Software Co-Verification Capabilities"

Mentor Graphics and GLOBALFOUNDRIES Collaborate on 20nm Fill Solutions Based on Calibre SmartFill

May 29, 2012

WILSONVILLE, Ore., May 29, 2012—Mentor Graphics Corporation (NASDAQ: MENT) today announced that GLOBALFOUNDRIES will use the SmartFill facilities of the Calibre® YieldEnhancer product to enable advanced fill techniques for 20nm manufacturing processes. The multi-layer fill analysis and cell-based fill generation capabilities of the SmartFill system help designers deal with complex fill interactions at advanced nodes with minimal impact on circuit performance. Moreover, Calibre SmartFill delivers greatly reduced post-fill GDS database size and faster runtimes compared to traditional dummy fill. Used with the design kit provided by GLOBALFOUNDRIES, Calibre SmartFill allows designers to meet IC fill constraints in a single … Read More → "Mentor Graphics and GLOBALFOUNDRIES Collaborate on 20nm Fill Solutions Based on Calibre SmartFill"

Kistler Piezoelectric Accelerometers Support Aircraft, Satellite, UAV, Helicopter and Missile Ground Vibration Testing

May 28, 2012

May 24, 2012, Novi, Michigan, USA – Kistler (www.kistler.com), a worldwide supplier of precision sensors, systems and instrumentation for the dynamic measurement of pressure, force, torque and acceleration, has announced the availability of its piezoelectric accelerometer technologies for cost-effective, high-accuracy support of aircraft, helicopter, rotorcraft, missile, satellite and unmanned aerial vehicle (UAV) ground vibration testing (GVT), as well as large-scale MIMO and SIMO aerospace structural monitoring.

Typical aerospace GVT requirements call for the use of high-performance piezoelectric accelerometers which offer a lower per channel cost, yet which are also … Read More → "Kistler Piezoelectric Accelerometers Support Aircraft, Satellite, UAV, Helicopter and Missile Ground Vibration Testing"

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