ASSET InterTech and Mentor Graphics IJTAG interoperability empowers two-way validation flow between chips and boards
Richardson, TX (Oct. 21, 2014 ? International Test Conference, Seattle, WA, Booth 305) ? Seamless interoperability between ASSET® InterTech (www.asset-intertech.com) and Mentor Graphics® Tessent® products for the IEEE P1687 Internal JTAG (IJTAG) embedded instrumentation standard will allow engineers to accurately debug and isolate issues in either a complex system-on-a-chip (SoC) or on the circuit board where the chip has been deployed. ASSET and Mentor are demonstrating IJTAG interoperability at the International Test Conference this week in Booths 304 and 305.
IJTAG resources, including embedded instruments and a network connecting them, are inserted into a chip with Mentor’s Tessent IJTAG solution. These … Read More → "ASSET InterTech and Mentor Graphics IJTAG interoperability empowers two-way validation flow between chips and boards"

