ATopTech’s Physical Implementation Tools Certified for TSMC’s 10nm FinFET Process
SANTA CLARA, CA – September 15, 2015 – ATopTech, a leader in next generation physical design solutions, has collaborated with TSMC and completed the certification of Aprisa™ and ApogeeTM, ATopTech’s place and route solutions, for TSMC V0.9 of 10nm FinFET process. Both companies continue to work on the completion of 10 nanometer certification of V1.0, targeting Q4, 2015. ATopTech also is included in the TSMC 10nm reference flow and is a member of TSMC’s Open Innovation Platform® (OIP).
Aprisa has natively supported full color-aware double patterning technology (DPT) since 20nm, which provided a good foundation for support of … Read More → "ATopTech’s Physical Implementation Tools Certified for TSMC’s 10nm FinFET Process"

