SANTA CLARA, CA – September 15, 2015 – ATopTech, a leader in next generation physical design solutions, has collaborated with TSMC and completed the certification of Aprisa™ and ApogeeTM, ATopTech’s place and route solutions, for TSMC V0.9 of 10nm FinFET process. Both companies continue to work on the completion of 10 nanometer certification of V1.0, targeting Q4, 2015. ATopTech also is included in the TSMC 10nm reference flow and is a member of TSMC’s Open Innovation Platform® (OIP).
Aprisa has natively supported full color-aware double patterning technology (DPT) since 20nm, which provided a good foundation for support of TSMC’s 10nm reference flow with full color-aware methodology. ATopTech collaborated with TSMC to identify and implement many enhancements in various parts of the tools for 10nm enablement, including full color-aware DPT routing, design rule checking, floorplanning, placement, routing and timing features. Those features will be included in the Aprisa/ Apogee tool release to customers and the Technology File can be downloaded directly from TSMC-Online.
ATopTech’s inclusion in the TSMC 10nm Reference Flow covers the following areas:
- Full coloring implementation
- Implementation with consideration of process variation
- Cell-level EM risk avoidance methodology: Implementation/fixing
- Concurrent CTS and metal EM avoidance
- MiM Cap insertion impact: Implementation
“ATopTech is ready for joint customers to design in 16FinFET+ and 10 nanometers,” said Jue-Hsien Chern, CEO of ATopTech. “As always, our ongoing relationship with TSMC and mutual customers allows us to deliver superior total turn-around time and quality of results for physical design projects.”
“ATopTech continues to work closely with TSMC to drive innovation for physical design,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. “Together, we are helping joint customers design in TSMC’s leading-edge technologies.”
ATopTech received a “Partner of the Year 2014” award at last year’s OIP Ecosystem Forum for “Joint Development of 16FinFET Plus Design Infrastructure,” and will participate in this year’s event that is being held in Santa Clara, CA on September 17, 2015.
About Aprisa
Aprisa is a complete place-and-route (P&R) engine, including placement, clock tree synthesis, optimization, global routing and detailed routing. The core of the technology is its hierarchical database. Built upon the hierarchical database are common “analysis engines,” such as RC extraction, DRC engine, and an advanced, extremely fast timing engine to solve the complex timing issues associated with OCV, signal integrity (SI) and multi-corner multi-mode (MCMM) analysis. Aprisa uses state-of-the-art multi-threading and distributed processing technology to further speed up the process. Because of this advanced architecture, Aprisa is able to deliver predictability and consistency throughout the flow, and hence faster total turn-around time (TAT) and best quality of results (QoR) for physical design projects.
About Apogee
Apogee is a full-featured, top-level physical implementation tool that includes prototyping, floorplanning, and chip assembly. The unified hierarchical database enables a much more streamlined hierarchical design flow. Unique in-hierarchy-optimization (iHO) technology helps to close top-level timing during chip assembly through simultaneous optimization at top level and at blocks, reducing the turnaround time for top-level timing closure from weeks to days.
About ATopTech
ATopTech, Inc. is the technology leader in IC physical design. ATopTech’s technology offers the fastest time to design closure focused on advanced technology nodes. The use of state-of-the-art multi-threading and distributed processing technologies speeds up the design process, resulting in unsurpassed project completion times. For more information, see www.atoptech.com
