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Jasper ActiveProp Automates Assertion-Based Verification for SoC Design

MOUNTAIN VIEW, Calif. – Jan. 27, 2011 – Jasper Design Automation today introduced ActiveProp(tm), an innovative new property synthesis tool that helps accelerate the adoption of assertion-based verification, including formal verification as well as simulation.

ActiveProp automatically generates high-level properties in industry-standard SystemVerilog Assertion (SVA) language, as well as human-readable reports, from RTL and simulation information. ActiveProp property synthesis helps expand the verification property set, increase functional coverage, and identify coverage holes, leading to higher-quality … Read More → "Jasper ActiveProp Automates Assertion-Based Verification for SoC Design"

Tanner EDA to Address Some of the Key Challenges Facing Analog Designers at DesignCon 2011

MONROVIA, California – January 25, 2011 – At DesignCon 2011, Tanner EDA, the catalyst for innovation for the design, layout and verification of analog and mixed-signal integrated circuits (ICs), will continue their focus on accelerating analog design in a panel session on process design kits (PDKs) for analog designers and in a presentation on breaking through the analog IC layout design bottleneck. DesignCon 2011 takes place from January 31st to February 3Read More → "Tanner EDA to Address Some of the Key Challenges Facing Analog Designers at DesignCon 2011"

Synopsys’ DesignWare DDR PHY Compiler Eases Integration of Memory Interface IP

MOUNTAIN VIEW, Calif., Jan. 26, 2011 /PRNewswire/ — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the immediate availability of the DesignWare® DDR PHY compiler, supporting DDR2, DDR3, LPDDR and LPDDR2 SDRAMs. The DesignWare DDR PHY compiler offers designers a web-based GUI to assemble a customized, high-performance DDR PHY for their system-on-chips (SoCs). The DesignWare DDR PHY compiler evaluates more than 60 variables and allows the evaluation of unlimited ‘what-if’ scenarios. The output of the PHY compiler is a customized hard DDR PHY … Read More → "Synopsys’ DesignWare DDR PHY Compiler Eases Integration of Memory Interface IP"

TI expands its MSP430™ MCU Value Line with 64 devices to give 8-bit developers more options with increased memory and capacitive touch capabilities

DALLAS, TX (January 25, 2011) – Continuing its commitment to provide more low-cost options to 8-bit developers, Texas Instruments Incorporated (TI) (NYSE: TXN) today announced 64 new ultra-low-power MSP430 Value Line microcontrollers (MCUs) that offer 16-bit performance at an 8-bit price. The new MSP430G2xx2 MCUs include integrated capacitive touch IOs, allowing developers to interface directly with capacitive touch pads, eliminating the need for additional hardware and components.  Additionally, the MSP430 MCU Value Line expansion provides extra package and memory options, providing developers with increased design flexibility. Supported by TI& … Read More → "TI expands its MSP430™ MCU Value Line with 64 devices to give 8-bit developers more options with increased memory and capacitive touch capabilities"

CAST adds H.264 Main Profile Video Encoder Core to Compression IP Family

January 26, 2011, Woodcliff Lake, NJ — Semiconductor intellectual property (IP) provider CAST, Inc. has expanded its suite of video and image compression IP with a new H.264 Main Profile Video Encoder core (http://www.cast-inc.com/ip-cores/video/h264-mp-e/).

The new core complements the Baseline Profile encoder CAST already offers by delivering better video compression with only a small increase in chip size. Both encoders are … Read More → "CAST adds H.264 Main Profile Video Encoder Core to Compression IP Family"

Mentor Graphics Calibre PERC Programmable Electrical Rule Checker Improves Fujitsu Chip Reliability

WILSONVILLE, Ore., January 25, 2011—Mentor Graphics Corporation (NASDAQ: MENT) today announced that Fujitsu Semiconductor Limited is now using the Calibre® PERC product for electrical rules checks that improve the correctness and reliability of its IC designs before committing to manufacturing. The product, which automates electrical checks based on user-defined rules, is designed to address customers’ need to improve reliability by identifying areas of vulnerability to catastrophic electrical failures in ICs during factory test, transport, and field operation. Among the specific checks being performed at Fujitsu Semiconductor are electrostatic discharge ( … Read More → "Mentor Graphics Calibre PERC Programmable Electrical Rule Checker Improves Fujitsu Chip Reliability"

Zoran Selects EVE’s ZeBu Emulation Platform

SAN JOSE, CALIF. –– January 25, 2011 –– Zoran Corporation has selected the ZeBu emulation platform from EVE, the leader in hardware/software co-verification, for the verification of its high-performance, multi-function peripheral system-on-chip (SoC) designs.

 ZeBu-Server was chosen after a thorough evaluation of its speed of execution, debugging capabilities and cost effectiveness, all critical factors for achieving thorough debugging of multi-million gate designs.  According to Zoran, ZeBu not only offers first-class performance but also superior debugging capabilities … Read More → "Zoran Selects EVE’s ZeBu Emulation Platform"

The University of Tokyo Picks Docea Power to Design NVM Architecture as Part of Japanese National Research Program

Tokyo, Japan and Grenoble, France – January 18, 2010 – Docea Power, the design-for-low-power company that delivers software for power and thermal analysis at the architectural level (ESL), announced today that its Aceplorer software has been selected by the University of Tokyo to model and optimize power consumption for new non-volatile … Read More → "The University of Tokyo Picks Docea Power to Design NVM Architecture as Part of Japanese National Research Program"

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