News – Page 1272 – EEJournal

IAR Systems adds powerful code analysis possibilities for Atmel 8-bit AVR developers

June 2, 2015

Uppsala, Sweden—June 2, 2015—IAR Systems® presents version 6.60 of its development tools IAR Embedded Workbench® for AVR. The update extends code analysis possibilities with the integration of static code analysis tools as well as stack usage analysis.

Version 6.60 of IAR Embedded Workbench for AVR adds support for IAR Systems’ static analysis add-on product C-STAT®. Completely integrated in the IAR Embedded Workbench IDE, C-STAT can perform numerous checks for compliance with rules as defined by the coding standards MISRA C:2004, MISRA C++:2008 and MISRA C:2012, as well as rules … Read More → "IAR Systems adds powerful code analysis possibilities for Atmel 8-bit AVR developers"

Brite Collaborates with SMIC and CEVA on Configurable IoT Solution Roadmap: Ultra Low-Power 55nm eFlash process and wireless baseband form basis for a China IoT ASIC Platform

June 2, 2015

Shanghai, China—June 2, 2015— Brite Semiconductor, an emerging ASIC design services firm headquartered in Shanghai, China, announced today the collaborative development of a design platform roadmap with key industry partners, including Semiconductor Manufacturing International Corporation (“SMIC”). The platform is designed to support Internet-of-Things (“IoT”) IC’s addressing the China market’s emerging needs for smart devices, wirelessly-connected to Cloud infrastructure.

Brite is developing its China IoT ASIC Platform based on SMIC’s 55nm low-leakage (LL) and ultra-low-power (ULP) process roadmap,which includes embedded flash (eFlash) memory. Over the design platform’s lifetime, these processes can significantly reduce operating … Read More → "Brite Collaborates with SMIC and CEVA on Configurable IoT Solution Roadmap: Ultra Low-Power 55nm eFlash process and wireless baseband form basis for a China IoT ASIC Platform"

Docea Power Reveals Aceplorer 4.0 and Thermal Profiler 4.0 to Speed Up Power and Thermal Management Policies Development and Validation at DAC52

June 1, 2015

Grenoble, France and San Jose, CA – May 29, 2015– Docea Power, the provider of virtual prototyping solutions for power and thermal, will reveal at the 52^nd Design Automation Conference (DAC) the latest releases of its Aceplorer and Thermal Profiler software tools. Docea Power will demonstrate new advances in power and thermal management modeling and simulation with Aceplorer 4.0 and Thermal Profiler 4.0 new solvers to speed up thermal verification.

Aceplorer 4.0 features a new programming interface, the PTM-API (Power and Thermal Management Application Programming Interface) for … Read More → "Docea Power Reveals Aceplorer 4.0 and Thermal Profiler 4.0 to Speed Up Power and Thermal Management Policies Development and Validation at DAC52"

TI introduces industry’s first fully integrated fluxgate sensor, signal conditioning and compensation coil driver IC, providing closed-loop current sensing

June 1, 2015

DALLAS (June 1, 2015) – Texas Instruments (TI) (NASDAQ: TXN) today introduced the industry’s first magnetic sensing integrated circuit (IC) with a fully integrated fluxgate sensor and compensation coil driver, along with all the required signal conditioning circuitry. Complete integration enables theDRV421 to provide best-in-class sensor accuracy and linearity, high dynamic range, and simpler system design compared to traditional Hall-effect-based closed-loop sensors. With the DRV421, system designers will be able to more easily develop magnetic closed-loop current sensors … Read More → "TI introduces industry’s first fully integrated fluxgate sensor, signal conditioning and compensation coil driver IC, providing closed-loop current sensing"

Synopsys’ IC Compiler II Used to Tape Out 28-nm-FD-SOI SoC

June 1, 2015

MOUNTAIN VIEW, Calif., June 1, 2015 /PRNewswire/ —

Highlights:

STMicroelectronics tapes out complex SoC design on 28-nm-FD-SOI technology using IC Compiler II
Fast throughput and analysis delivered 10X reduction in time-to-good-floorplan
5X faster implementation with 2X smaller memory footprint enabled breakthrough productivity while exceeding QoR goals

Synopsys, Inc. (Nasdaq: SNPS) today announced STMicroelectronics, a global semiconductor leader serving customers across the spectrum of electronics applications, has taped out their latest fully depleted silicon on insulator (FD-SOI) … Read More → "Synopsys’ IC Compiler II Used to Tape Out 28-nm-FD-SOI SoC"

8-Port IO-Link Reference Design Kit Speeds Development

June 1, 2015

MILPITAS, CA – June 1, 2015 – Linear Technology Corporation introduces an IO-Link (IEC 61131-9) reference design kit, which includes the DC2228A 8-port IO-Link master and DC2227A IO-Link device reference designs. With over 2.19 million IO-Link nodes installed worldwide, the growing demand for larger networks is addressed by the new reference design kit, which reduces IC count, development costs and time to market. Users can quickly evaluate an end-to-end IO-Link v1.1 system, complete with all required hardware, cables and software.

The DC2228A is a complete 8-port IO-Link master reference … Read More → "8-Port IO-Link Reference Design Kit Speeds Development"

Vesper Boosts Acoustic Performance with Piezoelectric MEMS Microphone

June 1, 2015

BOSTON – (June 1, 2015) – Vesper, the leader in advanced acoustic-sensing technology, today launched VM101, a piezoelectric MEMS (microelectromechanical systems) microphone that achieves 68 dB typical signal-to-noise ratio (SNR) — the highest acoustic-performance benchmark of any commercially available MEMS microphone.

As the first ultra-high SNR MEMS microphone, VM101 solves major performance issues facing consumer products manufacturers, enhancing the quality and clarity of audio capture to improve the voice user interface in smartphones, wearables, smart home appliances and Internet of Things (IoT) devices.

“Voice is expected to supplant touch as the dominant … Read More → "Vesper Boosts Acoustic Performance with Piezoelectric MEMS Microphone"

System Level Power Workshop at DAC

May 29, 2015

The System Level Power Workshop, co-organized and sponsored by Accellera Systems Initiative, the IEEE Design Automation Standards Committee (DASC) and Si2, will bring together members of both the user and standards communities to discuss the issues surrounding not only interoperability among tools and IP, but system level design and the creation of power models and their suitability at different levels of abstraction

When/Where
Tuesday, June 9, 2015

Design Automation Conference, Moscone Center, San Francisco, CA

1:15pm-4:30pm

Room 206</ … Read More → "System Level Power Workshop at DAC"

New AdvancedTCA A/D Converter Blade from VadaTech Boasts 8 Channels at 2.6 GSPS

May 29, 2015

Henderson, NV – May 28, 2015 – VadaTech, a manufacturer of embedded boards and complete application-ready platforms, has announced a new eight channel analog to digital converter (ADC) with 10-bit @ 2.6 GSPS performance. The board also has a single DAC, 14-bit @ 2.8 GSPS.

The ATC136 features a Virtex-7 FPGA and a 4-core PowerPC for very high performance and processing efficiency. There is 64-bit DDR3 memory on the FPGA (4 Gb) and the PowerPC (4 GB). There is also Flash memory and a Removable MicroSD card. The front panel ports include eight SMA, JTAG, dual RJ-45, Clock-In/Sync Out, and dual MicroUSB.

VadaTech offers … Read More → "New AdvancedTCA A/D Converter Blade from VadaTech Boasts 8 Channels at 2.6 GSPS"

Xilinx Collaborates with TSMC on 7nm for Fourth Consecutive Generation of All Programmable Technology Leadership and Multi-node Scaling Advantage

May 29, 2015

SAN JOSE, Calif., May 28, 2015 /PRNewswire/ — Xilinx, Inc. (NASDAQ:XLNX) announced that it has collaborated with TSMC on the 7nm process and 3D IC technology for its next generation of All Programmable FPGAs, MPSoCs, and 3D ICs. The technology represents the fourth consecutive generation where the two companies have worked together on advanced process and CoWoS 3D stacking technology, and will become TSMC’s fourth generation of FinFET technology. The collaboration will provide Xilinx a multi-node scaling advantage and build on … Read More → "Xilinx Collaborates with TSMC on 7nm for Fourth Consecutive Generation of All Programmable Technology Leadership and Multi-node Scaling Advantage"

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How Synopsys IP and TSMC’s N12e Process are Driving AIoT

May 8, 2024

Learn how artificial intelligence of things (AIoT) applications at the edge rely on TSMC's N12e manufacturing processes and specialized semiconductor IP.The post How Synopsys IP and TSMC’s N12e Process are Driving AIoT appeared first on Chip Design....