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VadaTech announces the FMC216 per VITA 57

September 13, 2017

Henderson, NV – September 11, 2017 – VadaTech, a leading manufacturer of integrated systems, embedded boards, enabling software and application-ready platforms, announces the FMC216 FPGA Mezzanine Card (FMC) per VITA 57. The FMC216 provides 12-bit ADC conversion at rate of up to 2.6 GSPS (ordering options available for 2.0 and 2.5 GSPS) and 14-bit DAC conversion at rates of up to 5.6 GSPS. The ADC section is based on AD9625 with 8 lanes of JESD204B routed to the FMC connector and full power bandwidth supporting IF sampling of signals up to 2 GHz. The DAC section uses AD9129 which can support multicarrier generation up to 4.2 GHz.

The … Read More → "VadaTech announces the FMC216 per VITA 57"

Synopsys IC Compiler II Certified for TSMC’s Advanced 7-nm FinFET Plus Node

Platform-Wide Certification for TSMC's Latest Advanced-Process Technology
September 13, 2017

MOUNTAIN VIEW, Calif., Sept. 11, 2017 /PRNewswire/ —

Highlights:

Renesas Electronics Delivers PLC Solution that Enables Voice Communication over Power Lines

Integrates Voice and Data Communications Over Building Power Distribution Networks with Reduced Wiring Costs
September 13, 2017

SANTA CLARA, Calif., September 13, 2017 — Renesas Electronics Corporation (TSE:6723), a premier supplier of advanced semiconductor solutions, today announced a new voice-over-power line communication (PLC) solution that enables both data communication and voice communication capabilities over existing power networks. The PLC solution reduces the amount of internal wiring required in buildings, enabling reduced implementation and maintenance costs for public address (PA) systems and security systems.

The new solution consists of Renesas’ PLC software modem (R9A06G037), which manages the PLC communications, and the RX651 microcontroller (MCU), which controls the audio codec processing. The new solution enables system manufacturers … Read More → "Renesas Electronics Delivers PLC Solution that Enables Voice Communication over Power Lines"

Open-Silicon Completes Successful Silicon Validation of High Bandwidth Memory (HBM2) IP Subsystem Solution

September 12, 2017

Silicon validation in TSMC’s 16nm FinFET technology and interoperability with HBM2 memory

  • Silicon-proven SoC solution enables next generation high bandwidth applications

Milpitas, CA, September 12, 2017 – Open-Silicon, a system-optimized ASIC solution provider, today announced it has successfully completed silicon validation of its High Bandwidth Memory (HBM2) IP subsystem in TSMC’s 16nm FinFET technology in combination with TSMC’s CoWoS® 2.5D silicon interposer technology and HBM2 memory. This full IP subsystem solution includes an HBM2 controller, PHY and interposer I/O, and completes the critical components needed for the successful integration of HBM2 memory … Read More → "Open-Silicon Completes Successful Silicon Validation of High Bandwidth Memory (HBM2) IP Subsystem Solution"

Qorvo® Multi-Channel IoT Transceiver is First Certified for Thread Protocol

System-on-Chip simultaneously supports Thread and ZigBee®, ensuring easy upgrades to tomorrow’s fully networked smart home
September 12, 2017

GREENSBORO, NC – September 11, 2017 – Qorvo® (Nasdaq:QRVO), a leading provider of innovative RF solutions that connect the world, today announced that its GP712 System-on-Chip is the first multi-channel Internet of Things (IoT) transceiver in the industry to be certified for the Thread protocol. With concurrent support for Thread and ZigBee® on different RF channels, the GP712 enables designers to use a single transceiver on their gateway products to simultaneously serve both IEEE802.15.4 implementations.

The GP712 incorporates Qorvo’s best-in-class range and low-power operation, as well as robust RF technology that limits interference. Its multi-channel, … Read More → "Qorvo® Multi-Channel IoT Transceiver is First Certified for Thread Protocol"

Synopsys and TSMC Collaborate to Develop DesignWare Foundation IP for Low-Power TSMC 40-nm eFlash Processes

Logic Libraries and Embedded Memories for TSMC 40LP and 40ULP eFlash Processes Improve Energy Efficiency for IoT Devices
September 12, 2017

MOUNTAIN VIEW, Calif., Sept. 12, 2017 /PRNewswire/ —

Highlights:

Renesas Electronics and Codeplay Collaborate on OpenCL™ and SYCL™ for ADAS Solutions

Open Standard Software Frameworks Facilitate Development Using Renesas’ R-Car SoCs to Deliver Computer Vision and Cognitive Processing
September 12, 2017

SANTA CLARA, Calif., September 12, 2017 ― Renesas Electronics Corporation (TSE:6723), a premier supplier of advanced semiconductor solutions, and Codeplay Software Ltd., experts in high-performance compilers and software optimization for multi-core processing, today announced their collaboration to deliver ComputeAorta™, Codeplay’s OpenCL open standard-based software framework for Renesas R-Car system-on-chips (SoCs). The framework will be available first on R-Car H3 as a proof of concept, then focusing on R-Car V3M and other R-Car SoCs of the Renesas autonomyTM Platform for advanced driving assistance system (ADAS) and automated driving. The new framework is designed to support software development for … Read More → "Renesas Electronics and Codeplay Collaborate on OpenCL™ and SYCL™ for ADAS Solutions"

New Cadence Allegro PCB DesignTrue DFM Technology Accelerates New Product Development and Introduction Process

Industry’s first comprehensive, real-time, in-design DFM technology enables PCB designers to avoid frustrating and time-consuming design-verify-fix iterations
September 12, 2017

SAN JOSE, Calif., September 12, 2017—Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced Cadence® Allegro® PCB DesignTrue DFM technology, the industry’s first solution to perform real-time, in-design design-for-manufacturing (DFM) checks integrated with electrical, physical and spacing design rule checks (DRCs). The innovative new technology, integrated into the Allegro PCB Editor, enables PCB designers to identify and correct errors immediately, long before manufacturing signoff. By finding errors earlier, design teams reduce rework, shorten design cycles and accelerate the new product development and introduction process, potentially saving at least one … Read More → "New Cadence Allegro PCB DesignTrue DFM Technology Accelerates New Product Development and Introduction Process"

Synopsys Successfully Tapes Out Broad IP Portfolio for TSMC 7-nm FinFET Process

DesignWare Foundation and Interface IP on TSMC 7-nm Process Technology Enables Faster Time-to-Market for Mobile, Automotive and High-Performance Computing SoCs
September 11, 2017

MOUNTAIN VIEW, Calif., Sept. 11, 2017 /PRNewswire/ —

Highlights:

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