Aldec shortens time of ASIC design prototype bring-up in FPGA with HES-DVM Proto mode
January 14, 2019
Henderson, Nevada, U.S.A. – January 14, 2019 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has unveiled the latest release of HES-DVM™, the company’s fully automated and scalable hybrid verification environment for SoC and ASIC designs. Release 2018.12 features enhancements to the level of automation in Prototyping mode plus the faster compilation of HDL to FPGA.
The new HES-DVM provides design partitioning and partition interconnection tools designed to meet the growing need for, and challenges associated with, FPGA prototyping; i.e. FPGAs used as a … Read More → "Aldec shortens time of ASIC design prototype bring-up in FPGA with HES-DVM Proto mode"
