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New standard allows stacked dies in 3D integrated circuits to connect with test equipment

An imec-initiated industry collaboration leads to publication of IEEE Std 1838TM for test access architectures for 3D integrated circuits (3D-ICs)

LEUVEN (Belgium), January 27, 2020 — This week, imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, announces that IEEE Std 1838TM-2019 – recently approved by the IEEE Standards Association – will be included in IEEE Xplore Digital Library from February 2020 onward. The new standard allows die makers to design dies which, if compliant to this standard, constitute, once stacked in a 3D-IC by a stack integrator, a consistent stack-level test access architecture. The standardization effort of the 3D-DfT (design-for-test) was initiated by imec.

3D-ICs exploit the vertical dimension for further integration by stacking dies on top of each other – as a way of keeping the momentum of Moore’s Law going. Eric Beyne, fellow and program director 3D System Integration at imec: “Advances in wafer processing and stack assembly technologies are creating a wealth of different stack architectures. This causes a sharp increase in the number of potential moments at which testing for manufacturing defects can be executed: pre-bond (before stacking), mid-bond (on partial stacks), post-bond (on complete stacks), and final test (on packaged 3D-ICs). Test equipment contacts ICs via its external interface through probe needles or at test socket. In a die stack, that external interface typically resides in the bottom die of the stack. For the test equipment to be able to deliver test stimuli to and receive responses from the various dies up in the stack, collaboration from the underlying dies is required to provide test access to the die currently being tested.”

An IEEE working group to standardize 3D-DfT was founded in 2011 by Erik Jan Marinissen, scientific director at imec in Leuven, Belgium and he served as its first chair. In recent years, Adam Cron, principal R&D engineer in the Design Group at Synopsys, has been the driving force as the current chair of the Working Group.

Amit Sanghani, vice president of engineering in the Design Group at Synopsys in Mountain View, California, USA stated: “3D-IC is an important technology to deliver the next wave of innovation as the industry scales past 7nm. Currently, die might come from different suppliers with disjoint DfT architectures. We believe standardizing 3D-DfT will benefit our customers by helping form a consistent stack-level DfT architecture and speeding time to market. Synopsys congratulates the IEEE P1838 Working Group on this milestone.”

The new standard consists of three main elements. (1) DWR, the die wrapper register: scan chains at the boundary of each die in the stack to enable modular testing of the internals of each die and of the interconnects between each pair of adjacent dies. (2) SCM, the serial control mechanism: a single-bit test control mechanism that transports instructions into the stack to control the test modes of the various die wrappers. (3) FPP, the optional flexible parallel port, i.e., a scalable multi-bit test access mechanism to efficiently transport up and down the die stack the large volumes of data typically associated with production test. While DWR and SCM are based on existing DfT standards, the FPP is truly novel to IEEE Std 1838™.

Wolfgang Meyer, senior group director R&D at Cadence Design Systems in San Jose, California, USA: “A DfT standard like IEEE Std 1838™ is important to the industry. Die makers know what they must provide, and stack integrators know they can expect. Moreover, EDA suppliers like Cadence can focus their tool support on architectures that are compliant with the new standard. It is good that there is some user-defined scalability with the standard as the 3D-IC field is so wide — a rigid ‘one-size-fits-all’ standard would not work.”

Junlin Huang, manager of a 150-person strong DfT team of HiSilicon in Shenzhen, China is a potential user of the new IEEE Std 1838™. Huang: “Per year, we do DfT insertion and automatic test pattern generation (ATPG) for tens of very large and complex digital chip designs in the most advanced technologies. Now, these products start using 3D technology and my DfT team needs to be ready to handle the associated DfT and ATPG challenges. IEEE Std 1838™ will help us with that task.”

From February 2020 onward, the new standard IEEE Std 1838™ will be available via IEEE Xplore to subscribers of IEEE standards as well as for purchase to everybody else.

About imec

Imec is a world-leading research and innovation hub in nanoelectronics and digital technologies. The combination of our widely acclaimed leadership in microchip technology and profound software and ICT expertise is what makes us unique. By leveraging our world-class infrastructure and local and global ecosystem of partners across a multitude of industries, we create groundbreaking innovation in application domains such as healthcare, smart cities and mobility, logistics and manufacturing, energy, and education. 

As a trusted partner for companies, start-ups, and universities we bring together more than 4,000 brilliant minds from over 97 nationalities. Imec is headquartered in Leuven, Belgium and has distributed R&D groups at a number of Flemish universities, in the Netherlands, Taiwan, USA, and offices in China, India and Japan. In 2018, imec’s revenue (P&L) totaled 583 million euro. Further information on imec can be found at www.imec-int.com.

Imec is a registered trademark for the activities of IMEC International (a legal entity set up under Belgian law as a “stichting van openbaar nut”), imec Belgium (IMEC vzw, supported by the Government of Flanders), imec the Netherlands (Stichting IMEC Nederland, part of Holst Centre which is supported by the Dutch Government), imec Taiwan (IMEC Taiwan Co.), imec China (IMEC Microelectronics (Shanghai) Co. Ltd.), imec India (Imec India Private Limited), and imec Florida (IMEC USA nanoelectronics design center).

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