industry news
Subscribe Now

New Cadence Joint Enterprise Data and AI Platform Dramatically Accelerates AI-Driven Chip Design Development

Highlights:
• The new Cadence platform is a critical big data analytics infrastructure that unifies massive data sets across all Cadence computational software
• Enables a new generation of Cadence AI-driven design and verification applications that dramatically improve productivity and PPA

SAN JOSE, Calif., September 13, 2022—Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the delivery of the Cadence Joint Enterprise Data and AI (JedAI) Platform, enabling a generational shift from single-run, single-engine algorithms in electronic design automation (EDA) to algorithms that leverage big data and artificial intelligence (AI) to optimize multiple runs of multiple engines across an entire SoC design and verification flow. The Cadence JedAI Platform enables engineers to glean actionable intelligence from massive volumes of chip design and verification data, opening the door to a new generation of AI-driven design and verification tools that dramatically improve productivity and power, performance and area (PPA). With the Cadence JedAI Platform, Cadence is unifying big data analytics across its AI platforms—Verisium™ verification, Cadence Cerebrus™ implementation, and Optimality™ system optimization—as well as third-party silicon lifecycle management systems.
With the new Cadence JedAI Platform, engineers can seamlessly manage both structured and unstructured data, including:

• Design data such as waveforms and coverage in functional verification, physical layout shapes, timing/power/voltage/variation analysis reports, design RTL, netlist and SDC specifications in design implementation
• Workload data such as runtime, memory usage and disk space usage, as well as metadata about the inputs to each job and dependencies between them
• Workflow data such as the tools and methodology used to create a design
The Cadence JedAI Platform makes it easier to manage design complexities associated with emerging consumer, hyperscale computing, 5G communications, automotive and mobile applications, and more. Customers using Cadence analog/digital/PCB implementation, verification, and analysis software—and even third-party applications—can use the Cadence JedAI Platform to unify and analyze all their big data analytics. Furthermore, the new platform is cloud-enabled, offering highly scalable compute resources in a secure design environment from top cloud providers.

“To enable the semiconductor industry to continue on its strong growth trajectory, it’s critical that the chip design process becomes much more efficient to keep pace with market demands,” said Pat Moorhead, CEO, founder and chief analyst at Moor Insights & Strategy. “Improving design processes through AI and big data analytics creates a clear benefit for engineering teams who can now extract key learnings from the vast quantities of EDA data right at their fingertips. The new Cadence JedAI Platform is designed to provide users with automated, intelligent design insights and the ability to greatly scale engineering team productivity.”

Customers using the Cadence JedAI Platform have access to the following benefits:

• Highly scalable: Enterprise-grade scalability and security, enabling design optimization across multiple runs, tools, users, designs, and EDA domains
• Actionable intelligence: Quickly compares metrics across different versions of the same design and/or multiple designs, providing recommended actions to improve PPA and increase verification coverage
• Workflow management technology: Integrated workflow management capability allows users to efficiently capture chip design methodologies and automatically transfer design data between projects through data connectors
• Customized analytics: Offers open industry-standard user interfaces such as Python, Jupyter Notebook and REST APIs, enabling designers to create custom analytics applications

“Meeting design targets requires a variety of analytics and significant design resources,” said Satoshi Shibatani, director, Digital Design Technology Department, Shared R&D EDA Division, Renesas. “By using the Cadence JedAI Platform’s big data analytics, we can retrieve necessary information and solve bottleneck issues quickly. We’re continuing to expand our AI collaboration with Cadence and use our extensive data effectively to our advantage to improve PPA as well as productivity across all stages of design and verification.”

“As chip design size and complexity has increased exponentially over the past decade, the volume of design and verification data has also increased with it,” said Dr. Venkat Thanvantri, VP of AI R&D at Cadence. “Previously, we saw that once a chip design project was completed, the valuable data was deleted to make way for the next project. There are valuable learnings in the legacy data, and the Cadence JedAI Platform makes it easy for engineering teams to access these learnings and apply them to future designs to deliver optimal engineering productivity and PPA and ultimately more predictable, higher quality product outcomes.”

The Cadence JedAI Platform supports the company’s Intelligent System Design™ strategy, which enables pervasive intelligence for design excellence. For more information, please visit www.cadence.com/go/jedaipr.

About Cadence
Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For eight years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.

Leave a Reply

featured blogs
Oct 6, 2022
The days of 'throwing it over the wall' are over. Heterogeneous integration is ushering in a new era of silicon chip design with collaboration at its core'”one that lives or dies on seamless interaction between your analog and digital IC and package design teams. Heterogeneo...
Oct 4, 2022
We share 6 key advantages of cloud-based IC hardware design tools, including enhanced scalability, security, and access to AI-enabled EDA tools. The post 6 Reasons to Leverage IC Hardware Development in the Cloud appeared first on From Silicon To Software....
Sep 30, 2022
When I wrote my book 'Bebop to the Boolean Boogie,' it was certainly not my intention to lead 6-year-old boys astray....

featured video

PCIe Gen5 x16 Running on the Achronix VectorPath Accelerator Card

Sponsored by Achronix

In this demo, Achronix engineers show the VectorPath Accelerator Card successfully linking up to a PCIe Gen5 x16 host and write data to and read data from GDDR6 memory. The VectorPath accelerator card featuring the Speedster7t FPGA is one of the first FPGAs that can natively support this interface within its PCIe subsystem. Speedster7t FPGAs offer a revolutionary new architecture that Achronix developed to address the highest performance data acceleration challenges.

Click here for more information about the VectorPath Accelerator Card

featured paper

Algorithm Verification with FPGAs and ASICs

Sponsored by MathWorks

Developing new FPGA and ASIC designs involves implementing new algorithms, which presents challenges for verification for algorithm developers, hardware designers, and verification engineers. This eBook explores different aspects of hardware design verification and how you can use MATLAB and Simulink to reduce development effort and improve the quality of end products.

Click here to read more

featured chalk talk

Hot-Swap and Power Protection -- Mouser Electronics and Analog Devices

Sponsored by Mouser Electronics and Analog Devices

When it comes to our always-on, critical systems we need to carefully consider power protection and maintainability. In this episode of Chalk Talk, Amelia Dalton and Dwight Larson investigate the issues that surround hot-plugging into an energized power supply, the best solutions to consider, what the different hot-swap circuit topologies look like for a variety of applications and why the MAX15090B/C with its innovative current foldback startup may be the best solution for your next design.

Click here for more information about Maxim Integrated MAX15090B/MAX15090C Hot Swap ICs