Several microcontroller vendors used the time around Embedded World 2025 to introduce some truly interesting devices. I’ve already written about the TI MSPM0 microcontroller family and the WCH CH570 microcontroller (see “TI says its MSPM0 is the world’s most teeny, tiny 32-bit microcontroller. It’s smaller than a grain of white rice and costs 16 cents.” and “A 10-cent RISC-V microcontroller from China? Why not?”), and now it’s Microchip’s turn with a new family of 8-bit AVR microcontrollers designed to help comply with advanced safety requirements including ASIL C and SIL 2.
You may be familiar with older Microchip AVR microcontrollers like the ATmega328P, which sits at the heart of the original Arduino Uno board. These new AVR microcontrollers designed for use in functional safety applications are far more advanced than the earlier ATmega328P. The AVR SD microcontroller family features a dual-core AVR processor. The two cores run in lockstep, and the microcontrollers in this family are equipped with plenty of uniquely configured memory (with ECC), a bountiful assortment of peripherals, and a tiny FPGA-like Configurable Custom Logic (CCL) block for application requirements that need faster processing than software alone can provide. These devices have an operating voltage range of 2.7V to 5.5V, and the smallest microcontroller in the AVR SD family sells for 93 cents each in 5,000-unit quantities. Microchip offers related functional safety resource kits that include an FMEDA (Failure Modes, Effects, and Diagnostic Analysis) software and help ensure compliance with ISO 26262 and IEC 61508 for $999 each.
A block diagram of the AVR SD microcontroller appears below.
Microchip’s new AVR SD microcontroller family features a dual-core processor that runs the two AVR cores in lockstep along with plenty of uniquely configured memory (with ECC), a bountiful assortment of peripherals, and a tiny FPGA for application requirements that need faster processing than software can provide. Image credit: Microchip
In the top center of the above block diagram, you’ll see the 8-bit dual-core AVR CPU. The original AVR RISC microcontroller architecture was developed in 1996 by Alf-Egil Bogen and Vegard Wollan, who were students at the Norwegian Institute of Technology. Atmel adopted the architecture for its microcontrollers in 1997. Microchip added the AVR microcontrollers to its portfolio when it purchased Atmel in 2016. This latest iteration of the 8-bit RISC architecture is a dual-core, 20MHz design that operates the two cores in lockstep to meet functional safety requirements in certain applications. This version of the AVR processor core also includes a hardware multiplier.
In keeping with the functional safety requirements, the on-chip memory (RAM and EEPROM) of the AVR SD microcontrollers is protected by ECC. The on-chip RAM capacity is 4 Kbytes for all family members. The on-chip EEPROM consists of several functional blocks. The three AVR32SD family members have 32 Kbytes of in-system-programmable Flash memory with ECC, while the three AVR64SD family members (designated as future products) will have 64 Kbytes of in-system-programmable Flash memory with ECC. In addition, all members of the AVR SD family have 256 bytes of EEPROM with ECC, 512 bytes of non-volatile memory (NVM) that can retain data while the rest of the chip is being erased and reprogrammed, and 256 bytes of non-volatile boot row memory for storing protected data such as cryptographic keys, which can be read only by code operating out of a special area of code memory called the Boot Section, which is accessed only during the microcontroller’s initial boot. The Boot Section resides in the lowest memory location addresses of the Flash EEPROM.
The rather long list of on-chip peripherals includes many of the usual suspects:
· A 6-channel event system that enables predictable, CPU-independent, inter-peripheral signaling
· One 16-bit Timer/Counter with three compare channels for PWM and waveform generation
· As many as four 16-bit Timer/Counters with input capture
· One 12-bit Timer/Counter optimized for power control
· One 16-bit Real-Time Counter (RTC) that can run from an external crystal or an internal oscillator
· As many as three USARTs with a fractional baud rate generator and auto-baud detection
· Two SPI ports with host/client operating modes
· Two I2C ports with simultaneous host/client operation and dual address matching
· Two 10-bit, 170ksamples/sec ADCs with independent voltage reference sources
· One 10-bit DAC
· Three analog comparators
· One or two zero crossing detectors
· Internal 1.024V, 2.048V, 4.096V, and 2.500V voltage references
In addition to these rather common on-chip peripherals, the AVR SD microcontrollers also incorporate Microchip’s CCL block with six programmable Lookup Tables (LUTs). Each CCL LUT can implement any 3-input logic function and can be used to implement a logic sequencer using an integrated flip-flop/latch distributed between each LUT pair. LUT inputs can be connected to an external device pin or to an internal event signal. The CCL block serves as a mini-FPGA inside of the microcontroller and could help to eliminate extra glue logic on a circuit board. A similar sort of mini-FPGA appeared in a Microchip PIC16F microcontroller family last year. (See “Tiny FPGA in Microchip’s latest PIC16 microcontroller adds real-time speed, sells for less than 50 cents.”)
According to Microchip’s AVR SD microcontroller data sheet: “The CCL can eliminate the need for external logic components and can also help the designer to overcome real-time constraints by combining Core Independent Peripherals (CIPs) to handle the most time-critical parts of the application independent of the CPU.” Personally, I suffer from a lack of imagination with respect to these CCL blocks with all of six LUTs, probably because I have a background with FPGAs that number LUTs in the hundreds to millions, but the AVR SD microcontroller data sheet does provide some examples. Here’s a diagram of the CCL block to help spur your imagination:
Each AVR SD microcontroller includes a 6-LUT Configurable Custom Logic (CCL) block that can implement logic functions involving external I/O pins and internal event signals. CCL blocks can also implement state machines and sequencers using integrated flip-flop/latches distributed among LUT pairs. Image credit: Microchip
Microcontroller silicon alone does not constitute a functionally safe design capability. Software will also play a very large role. To that end, Microchip provides software tools for the AVR SD microcontroller family. These tools include functional safety resource kits with FMEDA (Failure Modes, Effects, and Diagnostic Analysis) software that helps ensure compliance with ISO 26262 and IEC 61508. Each kit costs $999. Microchip also offers the MPLAB X IDE, MPLAB Code Configurator (MCC Melody), a license for the MPLAB XC8 certified functional safety compiler, and an ASIL C/SIL 2 compliant safety framework. The AVR32SD32 Curiosity Nano Evaluation Kit can get you started for the low, low price of $14.95.
