Mentor, a Siemens business, today introduced Tessent Connect – an innovative design-for-test (DFT) automation methodology that delivers intent-driven hierarchical test implementation that helps IC design teams achieve manufacturing test quality goals faster and with fewer resources compared to traditional DFT methods. As part of the Tessent Connect rollout, Mentor today also announced the Tessent Connect Quickstart program, offering detailed flow assessments from Mentor’s applications and consulting services engineers.
Today’s advanced IC designs can achieve very high defect coverage for manufacturing and in-system test by integrating dedicated on-chip infrastructure such as embedded compression, built-in self-test, and IEEE 1687 IJTAG networks. As IC designs grow in size and more of this on-chip IP is integrated, engineers have increasingly adopted hierarchical DFT approaches that break down the traditional DFT process into smaller, more manageable elements. However, retrofitting existing flows and automation to use hierarchical components and technologies often presents new sets of time-consuming and expensive inefficiencies.
Designed from the ground up to support hierarchical DFT, Mentor’s Tessent Connect automation approach helps eliminate these design inefficiencies. With Tessent Connect, IC designers interact with the Tessent software design tools using a higher level of abstraction, which describes the intended result rather than step-by-step instructions. The benefits of this abstraction-based approach include seamless collaboration across disparate DFT teams, plug-and-play reuse of IC components, significantly shorter turn-around times and the automation of many time-consuming setup, connectivity and pattern generation tasks.
An early adopter of Tessent Connect is eSilicon, a leading provider of FinFET application-specific integrated circuits (ASICs), market-specific IP platforms and advanced 2.5D packaging solutions. Leveraging the advanced automation of Tessent Connect, eSilicon recently improved IC DFT implementation cost while enabling system-level DFT testing and debug capabilities for a highly sophisticated next-generation ASIC.
“eSilicon uses Tessent Connect to help us meet our aggressive production schedules and deliver industry-leading ICs like those based on eSilicon’s neuASIC 7nm platform for machine learning,” said Joseph Reynick, director of DFT services at eSilicon. “As design complexity continues to grow, our system/OEM customers’ needs expand from just focusing on high quality IC manufacturing test to also providing effective in-system test and functional debug capabilities. With today’s complex 2.5D/3D devices, we are not shipping in volume until our chips are fully operational in our customers’ systems, including DFT and IP test. It would be very difficult to meet these challenges without the Tessent DFT portfolio and the efficiencies gained from Tessent Connect automation.”
Part of the Tessent Connect rollout, Mentor’s new Tessent Connect Quickstart program offers expertise in delivering customized insights and services that help IC design teams fully optimize and automate their DFT processes when using Tessent Connect.
“Our customers are continuously looking to reduce their test implementation costs as their design sizes grow and quality requirements become more stringent,” said Brady Benware, vice president and general manager for the Tessent product family at Mentor, a Siemens business. “With Tessent Connect and the corresponding Quickstart program, our customers are empowered with an accelerated and automated path to DFT sign-off.”
For more information about Mentor’s Tessent product line, please visit: https://www.mentor.com/products/silicon-yield/tessent/. In addition, attendees of the 2019 International Test Conference are invited to visit booth #401 for demonstrations of Tessent products and solutions.
