industry news
Subscribe Now

Mentor partners with Arm to help customers optimize the functional verification of sophisticated, next-generation ICs

Mentor, a Siemens business, today announced a partnership with Arm® to help integrated circuit (IC) designers optimize and streamline the functional verification of their Arm-based designs. With this collaboration, the Arm Design Reviews program now offers the expertise of Mentor’s top functional verification engineers to help customers optimize their Arm-based System-on-Chip (SoC) designs.

Arm’s new RTL Verification Design Review service, in collaboration with Mentor, helps IC design teams find the right balance of quality, advanced capability and cost for their Arm IP at the RTL level. The reviews can help customers enhance key design elements, including signal connectivity, system coherency, correct implementation and system performance.  

“Mentor and Arm have a strong track record of successful collaboration, and we are pleased to continue this long and fruitful relationship,” said Sam George, vice president, Mentor Consulting. “Mentor’s expertise in RTL design, combined with Arm’s extensive system design expertise, provides an invaluable wealth of knowledge for our shared customers.” 

Verification for a new IC can consume more than half of the total time spent on a typical SoC design. The efficient management of IC functional verification cycles grows increasingly critical as more complex designs are required to meet the demands of end-applications within the automotive, industrial equipment, medical and Internet of Things markets. The Arm and Mentor collaboration is intended to help mutual customers overcome these challenges by helping to optimize and dramatically shorten verification cycles.

With decades of expertise in the electronic design automation (EDA) market, Mentor is recognized globally for its expertise in IC functional verification technology. Many of the IC industry’s most innovative and successful products were developed using Mentor technology. 

“Verification is a crucial part of the SoC design process that cannot be overlooked,” said Ciarán Dunne, vice president and general manager, Partner Enablement at Arm. “Our new RTL Verification Design Review service offers the shared insight and expertise of Arm and Mentor, enabling customers to further improve the quality of their designs while shortening design cycles, time-to-market and reducing project risk.”

Additional information about Arm’s new RTL Verification Design Review service is available at http://www.arm.com/design-reviews

On November 4, Arm will conduct a free webinar entitled “Selecting the Best Design Verification Strategy for Your Design”. Featuring Mentor RTL experts, the webinar will take place at 10am GMT and again at 4pm GMT. Registration is open now. 

Leave a Reply

featured blogs
Mar 28, 2024
'Move fast and break things,' a motto coined by Mark Zuckerberg, captures the ethos of Silicon Valley where creative disruption remakes the world through the invention of new technologies. From social media to autonomous cars, to generative AI, the disruptions have reverberat...
Mar 26, 2024
Learn how GPU acceleration impacts digital chip design implementation, expanding beyond chip simulation to fulfill compute demands of the RTL-to-GDSII process.The post Can GPUs Accelerate Digital Design Implementation? appeared first on Chip Design....
Mar 21, 2024
The awesome thing about these machines is that you are limited only by your imagination, and I've got a GREAT imagination....

featured video

We are Altera. We are for the innovators.

Sponsored by Intel

Today we embark on an exciting journey as we transition to Altera, an Intel Company. In a world of endless opportunities and challenges, we are here to provide the flexibility needed by our ecosystem of customers and partners to pioneer and accelerate innovation. As we leap into the future, we are committed to providing easy-to-design and deploy leadership programmable solutions to innovators to unlock extraordinary possibilities for everyone on the planet.

To learn more about Altera visit: http://intel.com/altera

featured chalk talk

Package Evolution for MOSFETs and Diodes
Sponsored by Mouser Electronics and Vishay
A limiting factor for both MOSFETs and diodes is power dissipation per unit area and your choice of packaging can make a big difference in power dissipation. In this episode of Chalk Talk, Amelia Dalton and Brian Zachrel from Vishay investigate how package evolution has led to new advancements in diodes and MOSFETs including minimizing package resistance, increasing power density, and more! They also explore the benefits of using Vishay’s small and efficient PowerPAK® and eSMP® packages and the migration path you will need to keep in mind when using these solutions in your next design.
Jul 10, 2023
29,599 views