industry news
Subscribe Now

Mentor launches unique, end-to-end Xpedition High- Density Advanced Packaging flow

  • The Mentor® Xpedition® High-Density Advanced Packaging (HDAP) flow is the industry’s first comprehensive solution for the design and verification of today’s leading-edge IC package designs.
  • Industry-unique Xpedition Substrate Integrator tool enables rapid prototyping of heterogeneous substrate package assemblies.
  • The new Xpedition Package Design technology for physical package implementation ensures data synchronization for confident design sign-off and verification.
  • Integrated Mentor HyperLynx® technologies provide 2.5D/3D simulation models and design rule checking (DRC) to identify and resolve design errors with accuracy before tape-out.
  • Calibre® 3DSTACK technology enables complete signoff verification of a wide variety of 2.5D and 3D stacked die assemblies.

Mentor, a Siemens business, today announced the industry’s most comprehensive and productive solution for advanced IC package design, the Xpedition® High-Density Advanced Packaging (HDAP) flow. This comprehensive end-to-end solution, from rapid prototyping to GDS signoff, combines the Mentor® Xpedition, HyperLynx®, and Calibre® technologies. The new Mentor IC package design flow delivers faster, higher-quality results compared to existing HDAP methodologies and technologies. The Xpedition HDAP design environment provides early, rapid and accurate “what-if” prototype evaluations in just hours versus days or weeks compared to existing tools and processes, enabling exploration and optimization of HDAP designs before detailed implementation.

With emerging advanced packaging technologies such as fan-out wafer-level packaging (FOWLP), the worlds of IC design and packaging design are converging. This presents unique challenges to existing traditional design methodologies, driving a demand for new efficient processes, methodologies and design tools. Existing tools are inefficient – often failing when designs get to manufacturing. Mentor has addressed this problem with a unique HDAP solution comprising multi-substrate integration prototyping, and detailed physical implementation with foundry/OSAT-level verification and signoff.

“FOWLP projects a staggering expected growth rate of 82% from 2015 to 2020,” states Jan Vardaman, president of TechSearch International, Inc. “However, FOWLP is disruptive to the traditional design and manufacturing supply chain, and as with other high-density advanced packaging technologies, is driving the need for the co-design of devices and packages, and new flows, such as the Mentor HDAP solution.”

Unique HDAP Integration, Prototyping, and Package Design Technologies

The new HDAP flow introduces two unique technologies. The first, the Xpedition Substrate Integrator tool, is a graphical, rapid virtual prototyping environment which explores and integrates heterogeneous ICs with interposers, packages and PCBs. It provides fast and predictable assembly prototyping of complete cross-domain substrate systems through a rule-based methodology for optimal connectivity, performance, and manufacturability. The second new technology is the Xpedition Package Designer tool, a complete HDAP design-to-mask-ready GDS output solution, which manages the physical implementation of the package. The Xpedition Package Designer tool leverages the built-in HyperLynx design rule checking (DRC) for detailed in-design checking before signoff, and the HyperLynx FAST3D package solver provides package model creation. Direct integration with the Calibre tool then provides process design kit (PDK) signoff.

Integrated HyperLynx® Technology for In-Design Checking

The Xpedition HDAP flow is integrated with two Mentor HyperLynx technologies for 3D signal integrity (SI) and power integrity (PI), and in-process design rule checking (DRC). Package designers can simulate SI/PI 3D models using the HyperLynx FAST 3D field solver for extraction and analysis. The HyperLynx DRC tool easily identifies and resolves substrate-level DRC errors, typically finding 80-90% of the problems before final tape-out and sign-off verification.

Calibre® 3DSTACK Technology

When integrated with the Xpedition Package Designer tool, the Calibre 3DSTACK technology provides 2.5D/3D package physical verification. IC package designers can perform signoff design rule checking (DRC) and layout-versus-schematic (LVS) checking of complete multi-die systems at any process node, without breaking current tool flows or requiring new data formats, significantly reducing time to tapeout.

OSAT Alliance Program

Mentor has also launched an outsourced assembly and test (OSAT) Alliance program, a global design and supply chain resource for fabless customers to ease the adoption of emerging HDAP technologies. The OSAT Alliance Program includes proven design flows, tool kits, and recommended best practices for verification and signoff processes to create HDAP projects with the highest-quality results.

“The new Xpedition HDAP solution from Mentor brings together proven, industry-leading technologies from Xpediton, HyperLynx, and Calibre,” stated A.J. Incorvaia, vice-president and general manager of the Mentor Board Systems Division. “Companies are looking for a proven focused solution for FOWLP that combines foundry and OSAT design and manufacturing signoff support. The Xpedition HDAP flow provides our customers with a unified design and verification environment for foundry sign-off-ready designs.”

Product Availability

The Xpedition HDAP solution is available today. For additional product information, go to the website: https://www.mentor.com/pcb/ic-packaging. Mentor will also conduct Xpedition HDAP flow technical sessions at the Design Automation Conference (June 19-22, 2017 in Austin, Texas). To register: https://www.mentor.com/events/design-
automation-conference/focus/pcb

Leave a Reply

featured blogs
Nov 24, 2020
The ICADVM20.1 and IC6.1.8 ISR15 production releases are now available for download at Cadence Downloads . For information on supported platforms and other release compatibility information, see the... [[ Click on the title to access the full blog on the Cadence Community si...
Nov 23, 2020
It'€™s been a long time since I performed Karnaugh map minimizations by hand. As a result, on my first pass, I missed a couple of obvious optimizations....
Nov 23, 2020
Readers of the Samtec blog know we are always talking about next-gen speed. Current channels rates are running at 56 Gbps PAM4. However, system designers are starting to look at 112 Gbps PAM4 data rates. Intuition would say that bleeding edge data rates like 112 Gbps PAM4 onl...
Nov 20, 2020
[From the last episode: We looked at neuromorphic machine learning, which is intended to act more like the brain does.] Our last topic to cover on learning (ML) is about training. We talked about supervised learning, which means we'€™re training a model based on a bunch of ...

featured video

Improve SoC-Level Verification Efficiency by Up to 10X

Sponsored by Cadence Design Systems

Chip-level testbench creation, multi-IP and CPU traffic generation, performance bottleneck identification, and data and cache-coherency verification all lack automation. The effort required to complete these tasks is error prone and time consuming. Discover how the Cadence® System VIP tool suite works seamlessly with its simulation, emulation, and prototyping engines to automate chip-level verification and improve efficiency by ten times over existing manual processes.

Click here for more information about System VIP

featured paper

How semiconductor technologies have impacted modern telehealth solutions

Sponsored by Texas Instruments

Innovate technologies have given the general population unprecedented access to healthcare tools for self-monitoring and remote treatment. This paper dives into some of the newer developments of semiconductor technologies that have significantly contributed to the telehealth industry, along with design requirements for both hospital and home environment applications.

Click here to download the whitepaper

featured chalk talk

UWB: Because Location Matters

Sponsored by Mouser Electronics and Qorvo

While technologies like GPS, WiFi, and Bluetooth all offer various types of location services, none of them are well-suited to providing accurate, indoor/outdoor, low-power, real-time, 3D location data for edge and endpoint devices. In this episode of Chalk Talk, Amelia Dalton chats with Mickael Viot from Qorvo about ultra-wideband (UWB) technology, and how it can revolutionize a wide range of applications.

Click here for more information about Qorvo Ultra-Wideband (UWB) Technology