industry news
Subscribe Now

Lattice Shrinks Design Footprint and Cost, Boosts Reliability in Embedded Systems with Single Wire Aggregation IP Solution

Solution Lets Developers Reduce the Number of Physical Connectors Required to Link Components and Boards in Systems

HILLSBORO, OR – September 9, 2020 – Lattice Semiconductor Corporation (NASDAQ: LSCC), the low power programmable leader, today announced a Single Wire Aggregation (SWA) IP solution for reducing overall system size and BOM cost in industrial, consumer, and computing applications. The solution is a quick, easy, and innovative way for developers to use low power, small form factor Lattice FPGAs to dramatically reduce the number of board-to-board and component-to-component connectors in their embedded designs to increase reliability and reduce overall system footprint and cost.

The connectors used to link circuit boards and modules in electronic systems are costly, take up valuable space in devices with tight form factors, and over time can degrade and negatively impact system reliability. Routing signals between multiple connectors on space-constrained circuit boards can create design challenges that increase overall time-to-market.

“Developers are always looking for innovative ways to simplify and accelerate the development of embedded systems, while still maintaining the lowest BOM cost possible. Our new SWA solution meets all three of these needs by reducing the number of connectors in a system,” said Hussein Osman, Market Segment Manager, Lattice. “The solution is a strong fit for both novice and expert FPGA developers. Its pre-configured bitstreams help those new to FPGA-based design quickly configure an SWA application without requiring HDL coding experience, while the solution’s support for expanded parameterization makes it easy for FPGA experts to combine the Lattice SWA bitstreams with their own HDL code.”

Featuring the extremely low power and small size Lattice iCE40 UltraPlus™ FPGA, the SWA solution provides the hardware and software developers require to implement a single wire interface capable of aggregating multiple common I/O (I2C, I2S, UART and GPIO) data streams between components and circuit boards in a system. Lattice currently offers the following aggregated I/O configurations in pre-configured bitstreams for fast application prototyping.

  • Two I2S, an I2C peripheral, an I2C controller, and eight GPIO signals
  • Six I2C controller and two GPIO signals
  • One I2C controller and 12 GPIO signals
  • Three I2C controller, two I2C peripheral, and 15 GPIO signals
  • One I2S, one I2C controller, one I2C peripheral, and eight GPIO signals

Lattice customers requiring customized configurations can source them directly from Lattice technical support at no charge.

For more information, including how to purchase the SWA solution’s pre-configured bitstreams and hardware reference design, please visit: https://www.latticesemi.com/singlewire. The board is available for purchase at $249.00 from Lattice’s online store.

About Lattice Semiconductor

Lattice Semiconductor (NASDAQ: LSCC) is the low power programmable leader. We solve customer problems across the network, from the Edge to the Cloud, in the growing communications, computing, industrial, automotive, and consumer markets. Our technology, long-standing relationships, and commitment to world-class support lets our customers quickly and easily unleash their innovation to create a smart, secure and connected world.

For more information about Lattice, please visit www.latticesemi.com. You can also follow us via LinkedInTwitterFacebookYouTubeWeChatWeibo or Youku.

Leave a Reply

featured blogs
Apr 18, 2024
Analog Behavioral Modeling involves creating models that mimic a desired external circuit behavior at a block level rather than simply reproducing individual transistor characteristics. One of the significant benefits of using models is that they reduce the simulation time. V...
Apr 16, 2024
Learn what IR Drop is, explore the chip design tools and techniques involved in power network analysis, and see how it accelerates the IC design flow.The post Leveraging Early Power Network Analysis to Accelerate Chip Design appeared first on Chip Design....
Mar 30, 2024
Join me on a brief stream-of-consciousness tour to see what it's like to live inside (what I laughingly call) my mind...

featured video

MaxLinear Integrates Analog & Digital Design in One Chip with Cadence 3D Solvers

Sponsored by Cadence Design Systems

MaxLinear has the unique capability of integrating analog and digital design on the same chip. Because of this, the team developed some interesting technology in the communication space. In the optical infrastructure domain, they created the first fully integrated 5nm CMOS PAM4 DSP. All their products solve critical communication and high-frequency analysis challenges.

Learn more about how MaxLinear is using Cadence’s Clarity 3D Solver and EMX Planar 3D Solver in their design process.

featured chalk talk

Peak Power Introduction and Solutions
Sponsored by Mouser Electronics and MEAN WELL
In this episode of Chalk Talk, Amelia Dalton and Karim Bheiry from MEAN WELL explore why motors and capacitors need peak current during startup, the parameters to keep in mind when choosing your next power supply for these kind of designs, and the specific applications where MEAN WELL’s enclosed power supplies with peak power would bring the most benefit.
Jan 22, 2024
12,337 views