eSilicon, a leading provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, will deliver two DFT-related presentations at the International Test Conference (ITC) in Phoenix, Arizona on October 30 and 31, 2018.
Who
Joseph Reynick, director, DFT Solutions, eSilicon
What
Mentor’s Diamond Supporter Session
Test for the Autonomous Age
The presentations will focus on three key test challenges IC vendors face as they make the promises of the autonomous age a reality. Speakers: Joseph Reynick, eSilicon; Janusz Rajski, Mentor, A Siemens Business; and William Howell, Intel.
- DFT and IP test methods for a deep learning IC
- Achieving high test quality and fast yield ramps with advanced process technologies incorporating 3D transistors
- Strategies for meeting the requirements of a growing number of market segments like automotive that have strict quality and functional safety requirements
When/Where
Tuesday, 10/30/2018, 10:45 AM MST, immediately following the opening keynote session in the Ballroom
What
Special Session 3.1: Testing of Gigascale Designs
DFT Considerations and Flow for Large 2.5D/3D Devices
Traditional IC DFT engineers must expand their horizons to include the details of packaging, physical design, test hardware, and even board-level test techniques when working with large 2.5D/3D system–in-package (SiP) devices. The planning, implementation and test for such a SiP is discussed in this presentation. Our discussion will also include challenges, solutions and potential areas for new opportunities in supporting 2.5D/3D technologies in the future.
When/Where
Wednesday, 10/31/2018, 10:30 AM MST
About ITC
International Test Conference is the world’s premier conference dedicated to the electronic test of devices, boards and systems, covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement.
About eSilicon
eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Our neuASIC™ platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, artificial intelligence (AI) and 5G infrastructure markets. www.esilicon.com
