industry news
Subscribe Now

Industry Leaders Collaborate with Synopsys on Modeling Standards to Address Design Down to 2nm

Manufacturing Challenges and Need for Ultra-low Power Drive Extensions to Liberty and Interconnect Technology Standards

MOUNTAIN VIEW, Calif., Dec. 19, 2018 /PRNewswire/ —

Highlights:

  • Liberty extensions drive optimal implementation/QoR for ultra-low power applications
  • Extended parasitic extraction modeling for advanced process and device technologies
  • Collaboration with technology innovators drives modeling standards for 2nm and beyond
  • Technical advisory boards include Arm, NVIDIA, Qualcomm, TSMC, and others

Synopsys, Inc. (Nasdaq: SNPS) today announced that the Liberty Technical Advisory Board (LTAB) and Interconnect Modeling Technical Advisory Board (IMTAB) have ratified new modeling constructs to address timing and parasitic extraction challenges at process nodes down to two nanometers (nm). Mobile device requirements for ultra-low power and manufacturing challenges require new approaches to ensure the best accuracy at signoff while enabling design tools to optimize for the lowest power consumption. In addition, device architectures, mask, and patterning techniques at these nodes result in artifacts that must be modeled by new extensions in the interconnect technology file (ITF).

In power analysis, the Liberty standard has been enhanced to provide better insight into the assumptions use for computation of dynamic power values in the library models. Extraction modeling in the ITF file now addresses gate resistance for new device architectures, as well as patterning extensions on interconnect and trench contact structures.

“Through close collaboration with leading foundries and IDMs, we are able to keep modeling standards out in front of the next wave of advanced process nodes,” said Jacob Avidan, senior vice president of engineering in Synopsys’ Digital Group. “The latest modeling enhancements ratified by the Liberty and ITF technical advisory boards are essential to achieving timing and power requirements that allow our partners to bring the highest quality designs to market in the shortest time possible.”

All LTAB/IMTAB proposals have been quickly incorporated into Synopsys’ Fusion Design Platform™ to enable support for early technology adopters. Tools in the Fusion Design Platform include Design Compiler® synthesis, IC Compiler™ II place-and-route, StarRC® extraction, PrimeTime® signoff, and PrimePower power analysis.

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world’s 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you’re a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.

Leave a Reply

featured blogs
Jun 1, 2023
In honor of Pride Month, members of our Synopsys PRIDE employee resource group (ERG) share thoughtful lessons on becoming an LGBTQIA+ ally and more. The post Pride Month 2023: Thoughtful Lessons from the Synopsys PRIDE ERG appeared first on New Horizons for Chip Design....
Jun 1, 2023
It's been 40 years since Jim Solomon, Richard Newton and Alberto Sangiovanni-Vincentelli co-founded SDA Systems, a physical IC design tools company that became Cadence. Most want to measure this year as the 35 th birthday of Cadence, marked by the merger of SDA Systems and EC...
May 8, 2023
If you are planning on traveling to Turkey in the not-so-distant future, then I have a favor to ask....

featured video

Shift-left with Power Emulation Using Real Workloads

Sponsored by Synopsys

Increasing software content and larger chips are demanding pre-silicon power for real-life workloads. Synopsys profile, analyze, and signoff emulation power steps to identify and analyze interesting stimulus from seconds of silicon runtime are discussed.

Learn more about Synopsys’ Energy-Efficient SoCs Solutions

featured paper

EC Solver Tech Brief

Sponsored by Cadence Design Systems

The Cadence® Celsius™ EC Solver supports electronics system designers in managing the most challenging thermal/electronic cooling problems quickly and accurately. By utilizing a powerful computational engine and meshing technology, designers can model and analyze the fluid flow and heat transfer of even the most complex electronic system and ensure the electronic cooling system is reliable.

Click to read more

featured chalk talk

Direct Drive: Getting More Juice from Your JFET
Sponsored by Mouser Electronics and UnitedSiC
In this episode of Chalk Talk, Jonathan Dodge from UnitedSiC (now part of Qorvo) and Amelia Dalton discuss how you can take full advantage of silicon carbide JFET transistors. They delve into the details of these innovative transistors including what their capacitances look like, how you can control their speed and how you can combine the benefits of a cascode and a directly driven JFET in your next design.
Jun 29, 2022
38,829 views