Mountain View, Calif., JULY 21, 2017 – Flex Logixâ Technologies, Inc., the leading supplier of embedded FPGA IP and software, today released an application note highlighting the power of its EFLXâ embedded FPGA as a reconfigurable accelerator. FPGA can provide parallel processing that dramatically improves performance over the serial processing of MPUs. The reconfigurability of embedded FPGA enables it to accelerate more than one task as workloads require or as different customers require for their specific applications.

“Performance is critical in applications such as MCU, SoC and data centers,” said Tony Kozaczuk, Director of Architecture Solutionsfor Flex Logix. “The ability to accelerate critical code by one or two orders of magnitude is something every chip designer should be evaluating today. This new app note provides them with the exact implementations for connecting EFLX to common buses and multiple detailed performance comparisons needed to begin adopting this powerful technology platform.”

About the App Note

The new app note, which is available at this link, details how to connect embedded FPGA to AXI and AHB buses and shows several examples of reconfigurable accelerators, giving area and performance (in 16nm – contact Flex Logix for 28nm or other process nodes) and showing how much faster the embedded FPGA accelerators are than a typical ARM processor.

About Flex Logix

Flex Logix, founded in March 2014, provides solutions for reconfigurable RTL in chip and system designs using embedded FPGA IP cores and software. The company’s technology platform delivers significant customer benefits by dramatically reducing design and manufacturing risks, accelerating technology roadmaps, and bringing greater flexibility to customers’ hardware. Flex Logix has raised more than $12 million of venture capital. It is headquartered in Mountain View, California and has sales rep offices in China, Europe, Israel, Japan, Taiwan and Texas. More information can be obtained at http://www.flex-logix.com or follow on Twitter at @efpga.