industry news
Subscribe Now

eSilicon Tapes Out 7nm neuASIC IP Platform Test Chip

Chip validates latest release of IP to support artificial intelligence ASICs

SAN JOSE, Calif. — May 7, 2019 — eSilicon, a leading provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today the tapeout of a 7nm test chip to validate the latest neuASIC™ IP platform release. eSilicon’s neuASIC IP platform provides a library of IP that supports a wide range of functions found in artificial intelligence applications. The IP is verified to be compatible and supports algorithm-specific customization as well as a validated integration architecture through eSilicon’s ASIC Chassis.

IP on the test chip includes specialized memory and compute blocks to support near-memory compute applications. These include specialized low power memory for interfacing with multiply-accumulate functions (MACs) as well as large embedded SRAMs supporting multiple ports. The large (GIGA) memory supports WAZPS (word all zero power saving) and various sleep modes for standby power reduction. The compute blocks include several MAC blocks, low power standard cells, transpose memory functions and a convolutional neural network engine. Low-power data movement IP (cross-bar) are also included as well as IP for support functions such as GPIO, PLL and BIST.

“Our neuASIC IP platform has received a very strong reception,” said, Patrick Soheili, vice president, business and corporate development at eSilicon. “Some of the largest consumers of AI technology in the world, as well as many high-profile AI startups have engaged with us to dig deeper into our neuASIC IP platform. This new test chip will provide silicon data to support that process.”

You can learn more about eSilicon’s neuASIC IP platform here, or contact your eSilicon sales representative directly or via sales@esilicon.com.

About eSilicon
eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Our neuASIC™ platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, AI and 5G infrastructure markets. www.esilicon.com

Leave a Reply

featured blogs
May 19, 2019
https://youtu.be/cTEPUNpqcRg Made at Samsung HQ (camera Sean) Monday: Bob Smith on ESD Alliance, ES Design West...with Wine Tuesday: After Meltdown and Spectre Wednesday: Vision Q7 DSP: Real-Time... [[ Click on the title to access the full blog on the Cadence Community site....
May 17, 2019
The Design Automation Conference (DAC) is the premier conference for automated electronics design and verification technology. For 2019, DAC returns to sunny Las Vegas, Nevada at the Las Vegas Convention Center from June 2-5, 2019. We'€™ve packed each day full of exciting ...
May 17, 2019
In the days of old we looked into the “green” for guidance on how much further down into the world of miniaturization we could go. What is the green you ask? I am talking about the substrate that has served us all well for many years; the PCB. We are at a crossroa...
Jan 25, 2019
Let'€™s face it: We'€™re addicted to SRAM. It'€™s big, it'€™s power-hungry, but it'€™s fast. And no matter how much we complain about it, we still use it. Because we don'€™t have anything better in the mainstream yet. We'€™ve looked at attempts to improve conven...