industry news
Subscribe Now

DDC-I and LDRA Accelerate Compliance for Multicore Aerospace Systems

Integration delivers powerful, efficient means of developing, verifying, and hosting production code in safety-critical cockpit environments requiring software verified to the guidance of DO-178C/ED-12C

Phoenix, AZ – August 18, 2021 – DDC-I, a leading supplier of software and professional services for mission- and safety-critical applications, today announced an enhanced integration between the Deos safety-critical RTOS and LDRA’s automated software verification, source code analysis, and unit testing tools for aerospace and defense applications. The integrated solution enables avionic system manufacturers to quickly and cost-effectively develop, debug, test, and deploy software that can be readily verified to the most demanding guidance of DO-178C/ED-12C Design Assurance Level (DAL A).

With the completion of this integration, the latest LDRA tool suite now supports the latest version of DDC-I’s Deos™ safety-critical real-time operating system (RTOS) with its SafeMC™ multicore technology. The LDRA tool suite provides enhancements for source code static analysis, software dynamic analysis (including MC/DC coverage on the host and target), and software unit testing on the host and target. Together, these enhancements improve code quality, safety, and security, as well as reduce testing time and cost. They also help developers manage and achieve compliance for increasingly complex safety-critical cockpit applications that utilize emerging technologies like modular avionics and multicore processors to build safer, more economical, more capable aircraft. 

“The integration of Deos with the LDRA tool suite gives avionics developers the platform they need for rapid prototyping, testing, certification and deployment of modular, reusable, safety-critical applications that comply with DO-178C and FACE,” said Greg Rose, vice president of marketing and product management at DDC-I. “The updated Deos and LDRA integration should prove especially attractive to developers who want to utilize the latest multicore technology while addressing worst-case execution requirements as defined in the FAA’s CAST-32A position paper for Multi-core Processors.”

“Proving the avionics system is properly partitioned to avoid interference from competing cores is critical, yet it’s a nearly impossible challenge without the proper development and testing tools,” said Ian Hennell, Operations Director, LDRA. “Using the LDRA/DDC-I integration, developers can ensure the software is safe and meets the most demanding avionics standards such as DO-178C and the Future Airborne Capability EnvironmentTM (FACE) Technical Standard.”

To facilitate the development and testing of software that conforms with safety-critical standards such as DO-178C/ED-12C, and portability and interoperability standards such as the FACE Technical Standard, the integrated Deos/LDRA integration provides: 

  • Full source-code coverage analysis (under Deos SafeMC). 
  • An efficient unit testing harness for fully automated unit and regression testing (also under Deos with SafeMC). 
  • The ability to analyze and visualize coding standards compliance within the OpenArbor IDE. 
  • Support for x86, PowerPC, and ARM single and multicore processors.
  • Compliance with industry- and user-defined coding standards such as MISRA and CERT.
  • Automated test case, harness and stub generation for robustness testing with the LDRA tool suite.
  • Automatic production of software certification and approval evidence underpinned by LDRA’s ISO 9001:2015 certified Quality Management System, and the LDRA tool suite’s TÜV SÜD and SGS-TÜV Saar certification.

Deos is a safety-critical embedded RTOS that employs patented cache partitioning, memory pools, and safe scheduling to deliver higher CPU utilization than any other certifiable safety-critical COTS RTOS on multi-core processors. First certified to DO-178 DAL A in 1998, Deos provides a FACE™ Conformant Safety Base Profile that features hard real-time response, time and space partitioning, and both ARINC-653 and POSIX interfaces. 

SafeMC™ technology extends Deos’ advanced capabilities to multiple cores, enabling developers of safety-critical systems to achieve best in class multi-core performance without compromising safety-critical task response and guaranteed execution time. SafeMC employs a bound multiprocessing (BMP) extension of the symmetric multiprocessing architecture (SMP), safe scheduling, and cache partitioning to minimize cross-core contention and interference patterns that affect the performance, safety criticality and certifiability of multi-core systems. These features enable avionics systems developers to address issues that could impact the safety, performance and integrity of a software airborne system executing on Multi-Core Processors (MCP), as specified by the Certification Authorities Software Team (CAST) in its Position Paper CAST-32A for Multi-core Processors.

About DDC-I, Inc.

DDC-I, Inc. is a global supplier of real-time operating systems, software development tools, custom software development services, and legacy software system modernization solutions, with a primary focus on mission- and safety-critical applications. DDC-I’s customer base is an impressive “who’s who” in the commercial, military, aerospace, and safety-critical industries. DDC-I offers safety-critical real-time operating systems, compilers, integrated development environments and run-time systems for C, C++, and Ada application development. For more information regarding DDC-I products, contact DDC-I at 4545 E. Shea Blvd, Phoenix, AZ 85028; phone (602) 275-7172; fax (602) 252-6054; e-mail sales@ddci.com or visit04http://www.ddci.com/pr2104.

Leave a Reply

featured blogs
Mar 28, 2024
The difference between Olympic glory and missing out on the podium is often measured in mere fractions of a second, highlighting the pivotal role of timing in sports. But what's the chronometric secret to those photo finishes and record-breaking feats? In this comprehens...
Mar 26, 2024
Learn how GPU acceleration impacts digital chip design implementation, expanding beyond chip simulation to fulfill compute demands of the RTL-to-GDSII process.The post Can GPUs Accelerate Digital Design Implementation? appeared first on Chip Design....
Mar 21, 2024
The awesome thing about these machines is that you are limited only by your imagination, and I've got a GREAT imagination....

featured video

We are Altera. We are for the innovators.

Sponsored by Intel

Today we embark on an exciting journey as we transition to Altera, an Intel Company. In a world of endless opportunities and challenges, we are here to provide the flexibility needed by our ecosystem of customers and partners to pioneer and accelerate innovation. As we leap into the future, we are committed to providing easy-to-design and deploy leadership programmable solutions to innovators to unlock extraordinary possibilities for everyone on the planet.

To learn more about Altera visit: http://intel.com/altera

featured chalk talk

Power High-Performance Applications with Renesas RA8 Series MCUs
Sponsored by Mouser Electronics and Renesas
In this episode of Chalk Talk, Amelia Dalton and Kavita Char from Renesas explore the first 32-bit MCUs based on the new Arm® Cortex® -M85 core. They investigate how these new MCUs bridge the gap between MCUs and MPUs, the advanced security features included in this new MCU portfolio, and how you can get started using the Renesas high performance RA8 series in your next design. 
Jan 9, 2024
11,334 views