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CEA-Leti Demonstrates Breakthrough Architecture for HPC Devices Using Gate-All-Around Nanosheet Fabrication Process

Virtual Presentation During VLSI 2020 Details Transistors’ Performance And Power-Use Advantages Versus FinFET Devices

GRENOBLE, France – June 15, 2020 – CEA-Leti has demonstrated fabrication of a new gate-all-around (GAA) nanosheet device as an alternative to FinFET technology targeting high-performance (HPC) applications such as smartphones, laptops, and mobile systems with data collection and processing involving low-power and high-speed operation.

Institute researchers fabricated GAA nanosheet transistors with seven levels of stacked silicon channels, more than twice as many as state-of-the-art today, with widths ranging from 15nm to 85nm. The results were summarized in the paper, “7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing”, presented virtually during the 2020 Symposia on VLSI Technology & Circuits, June 14-19.

CEA-Leti scientist Sylvain Barraud, one of the authors of the paper, said the seven levels of stacked nanosheet GAA transistors fabricated using a replacement metal gate process, inner spacer and self-aligned contacts show excellent gate controllability with extremely high current drivability (3mA/μm at VDD=1V), and a three-x improvement in drain current over the usual two levels stacked nanosheet GAA transistors.

“By increasing the number of stacked-channels, we increase the effective width of the device for a given layout footprint,” he explained. “Increasing the effective width induces higher drive current. This is why the DC performance of our devices is better than leading-edge devices.”

Barraud said CEA-Leti’s demonstration was based on a “replacement metal-gate” process developed for FinFET.

“We added specific modules for GAA structures on this FinFET route and we showed that for the same surface occupation we can propose an alternative to FinFET technology due to a gate-all-around configuration,” he said. “In fact, GAA structures offer many advantages over FinFET, such as better gate control and higher DC performance, thanks to higher effective channel width. In addition, the wide range of variable nanosheet widths allows more design flexibility, which is not possible for FinFET because of its discrete number of fins.”

About CEA-Leti (France)

Leti, a technology research institute at CEA, is a global leader in miniaturization technologies enabling smart, energy-efficient and secure solutions for industry. Founded in 1967, CEA-Leti pioneers micro-& nanotechnologies, tailoring differentiating applicative solutions for global companies, SMEs and startups. CEA-Leti tackles critical challenges in healthcare, energy and digital migration. From sensors to data processing and computing solutions, CEA-Leti’s multidisciplinary teams deliver solid expertise, leveraging world-class pre-industrialization facilities. With a staff of more than 1,900, a portfolio of 3,100 patents, 10,000 sq. meters of cleanroom space and a clear IP policy, the institute is based in Grenoble, France, and has offices in Silicon Valley and Tokyo. CEA-Leti has launched 65 startups and is a member of the Carnot Institutes network. Follow us on www.leti-cea.com and @CEA_Leti.

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