industry news
Subscribe Now

Cadence Quantus FS Solution, a 3D Field Solver, Achieves Certification for Samsung Foundry’s SF4, SF3E and SF3 Process Technologies

Highlights:

• Quantus FS solution optimized to support Samsung Foundry’s advanced technologies, delivering tighter parasitic extraction accuracy versus foundry criteria
• Accelerates customer deployment of Quantus FS for library IP creation, using Samsung Foundry’s SF4, SF3E and SF3 process technologies

SAN JOSE, Calif., January 25, 2023 —Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Samsung Foundry has certified the Cadence® Quantus FS solution for its SF4, SF3E and SF3 process technologies. During the Samsung Foundry certification process, the Quantus FS solution successfully demonstrated improved accuracy (tighter mean and standard deviation) versus foundry criteria, ensuring customers can achieve optimal design accuracy and performance. In addition, the certification included verification of capacitance and resistance of BEOL and FEOL, wire via resistance variation and litho bias modeling. Customers can immediately deploy the Quantus FS solution—for library IP characterization, AMS and interface IP, sensors, high-frequency analog and mixed-signal designs, and critical nets in all custom/analog designs—and sign off with confidence.

Included with Cadence’s Quantus Extraction Solution, the Quantus FS solution is a random-walk field solver, utilizing a massively parallel architecture that handles the largest designs, provides faster throughput and linearly scales up to 1000s of CPUs. The built-in 3D capacitance field solver is cloud-ready and production-proven, offering a flexible, scalable modeling platform that enables faster implementation of the Samsung Foundry’s advanced process technologies such as SF4, SF3E and SF3. The Quantus Extraction Solution and the Quantus FS solution are part of Cadence’s broader digital full flow and support the Cadence Intelligent System Design strategy, enabling system-on-chip (SoC) design excellence. For more information on the Quantus FS solution, please visit www.cadence.com/go/quantusfscertpr.

“Our continued collaboration with Cadence has focused on delivering novel technologies to our mutual customers at advanced process technologies,” said Sungjae Lee, vice president of the Design Enablement team at Samsung Foundry. “Cadence’s understanding of the complex Gate-All-Around (GAA) modeling features combined with its deep engineering expertise, agility and collaborative approach is very complementary to our own approach in working with our customers. Cadence delivered on all of our accuracy and performance requirements, demonstrating tighter correlation with our golden reference data in a timely manner.”

“The best way to support our customers is to bring innovative products to market that provide efficiencies and speed time to market,” said Vivek Mishra, corporate vice president in the Digital and Signoff Group at Cadence. “We collaborated with Samsung Foundry during the initial technology development process to ensure all the requirements were met and implemented in the Quantus FS solution for easy, early customer adoption of the process technologies. The successful completion of the certification process is a win-win for Samsung Foundry and Cadence as well as for our mutual customers.”

About Cadence
Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For eight years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.

Leave a Reply

featured blogs
Mar 24, 2023
With CadenceCONNECT CFD less than a month away, now is the time to make your travel plans to join us at the Santa Clara Convention Center on 19 April for our biggest CFD event of the year. As a bonus, CadenceCONNECT CFD is co-located with the first day of CadenceLIVE Silicon ...
Mar 23, 2023
Explore AI chip architecture and learn how AI's requirements and applications shape AI optimized hardware design across processors, memory chips, and more. The post Why AI Requires a New Chip Architecture appeared first on New Horizons for Chip Design....
Mar 10, 2023
A proven guide to enable project managers to successfully take over ongoing projects and get the work done!...

featured video

First CXL 2.0 IP Interoperability Demo with Compliance Tests

Sponsored by Synopsys

In this video, Sr. R&D Engineer Rehan Iqbal, will guide you through Synopsys CXL IP passing compliance tests and demonstrating our seamless interoperability with Teladyne LeCroy Z516 Exerciser. This first-of-its-kind interoperability demo is a testament to Synopsys' commitment to delivering reliable IP solutions.

Learn more about Synopsys CXL here

featured chalk talk

Introduction to Bare Metal AVR Programming
Sponsored by Mouser Electronics and Microchip
Bare metal AVR programming is a great way to write code that is compact, efficient, and easy to maintain. In this episode of Chalk Talk, Ross Satchell from Microchip and I dig into the details of bare metal AVR programming. They take a closer look at the steps involved in this kind of programming, how bare metal compares with other embedded programming options and how you can get started using bare metal AVR programming in your next design.
Jan 25, 2023
8,728 views