industry news
Subscribe Now

Agile Analog launches first complete RISC-V analog IP subsystem at RISC-V Summit Europe

Accelerating time to market for RISC-V IoT applications

Cambridge, UK, 5 June 2023. Agile Analog, the customizable analog IP company, is launching the first complete analog IP subsystem for RISC-V applications at the RISC-V Summit Europe in Barcelona (5-9 June). The initial subsystem includes all the analog IP required for a typical battery powered IoT system, including a power management unit (PMU), a sleep management unit (SMU), and data converters. This unique, process agnostic, customizable and digitally wrapped analog IP subsystem will help solve many of the issues that System on Chip (SoC) designers currently encounter, as it pairs with a RISC-V core to form a complete solution.

Chris Morrison, Director of Product Marketing at Agile Analog, explains:

“The RISC-V architecture is enabling a surge of new SoC product developments, and the demand for more accessible and configurable IP solutions is increasing. One of the major challenges that digital chip designers face is in integrating the analog circuitry to support their SoC designs.”

Chris adds: “With our RISC-V analog IP subsystem, it’s possible to access the appropriate analog IP for a specific process and foundry. This can then be integrated seamlessly with digital IP from a digital IP provider in the RISC-V space, simplifying chip design and accelerating the time to market for new RISC-V IoT applications. As with all of the Agile Analog IP, this subsystem is customizable to give the exact feature set required for the application.”

Traditional analog IP has been a major bottleneck for many years, with limited options available, and chip designers have struggled to integrate multiple analog IP blocks, often from multiple vendors. The design and verification of the mixed-signal boundary between analog and digital has been a particularly daunting task, as this is renowned for being time-consuming and expensive, requiring specialist knowledge and tools. However, as a result of Agile Analog’s unique technology and novel digitally wrapped approach, these integration and verification challenges can be addressed and promptly resolved by Agile Analog on behalf of the customer.

This new analog IP subsystem is verified in both analog and digital environments, connects directly to the MCU’s peripheral bus, and is supplied with a SystemVerilog model for easy integration into an SoC’s existing digital verification environment.

Calista Redmond, CEO of RISC-V International, comments:

“RISC-V is already seen in over 10 billion cores globally, and the RISC-V ecosystem is flourishing. It’s really important that there are innovative solutions like this to help chip designers in our community to fast-track the delivery of exciting new RISC-V IoT applications.”

Agile Analog will be exhibiting and presenting at the RISC-V Summit Europe 2023.

Agile Analog’s initial RISC-V subsystem macro for IoT applications is available now consisting of the following sub-blocks:


The agilePMU Subsystem is an efficient and highly integrated power management unit for SoCs/ASICs. Featuring a power-on-reset, multiple low drop-out regulators, and an associated reference generator, this is designed to ensure low power consumption while providing optimal power management capabilities. Equipped with an integrated digital controller, this subsystem offers precise control over start-up and shutdown, supports supply sequencing, and allows for individual programmable output voltage for each LDO. Status monitors provide real-time feedback on the current state of the subsystem, ensuring optimal system performance.


The agileSMU Subsystem is a low power integrated macro consisting of the essential IP blocks required to securely manage waking up a SoC from sleep mode.  Typically containing a programmable oscillator for low frequency SoC operation and RTC, a number of low power comparators which can be used to initiate the wake-up sequence, and a power-on-reset which provides a robust, start-up reset to the SoC. Equipped with an integrated digital controller, this subsystem offers precise control over wake-up commands and sequencing. Status monitors provide real-time feedback on the current state of the subsystem, ensuring optimal system performance over the full product lifecycle.


The agileSensorIF Subsystem is a low power integrated macro providing all the analog required to interface with external sensors. Featuring two up-to 12-bit and 64 MSPS SAR ADCs, a 12-bit DAC and multiple programmable comparators, this sensor interface provides all the connections needed to interface with the outside world. Integrated programmable gain amplifiers and buffers support a wide range of external sensors and systems. It is equipped with an integrated digital controller and status monitors to provide real-time feedback on the current state of the subsystem, ensuring optimal system performance over the full product lifecycle.

Agile Analog company profile:

Agile Analog™ is transforming the world of analog IP with Composa™, its innovative, configurable, multi-process analog IP technology. Headquartered in Cambridge, UK, with a growing number of partners and customers across the globe, Agile Analog has developed a unique way to automatically generate analog IP that meet the customer’s exact specifications on almost any process from any foundry. The company provides a wide and ever-expanding selection of analog IP and subsystems for power management, data conversion, IC health and monitoring, security, and always-on domains. Agile Analog’s novel approach utilizes tried and tested analog circuits within its Composa library to create customized and verified analog IP solutions. This reduces the time to market and increases quality, helping to accelerate innovation in semiconductor design.

Leave a Reply

featured blogs
May 8, 2024
Learn how artificial intelligence of things (AIoT) applications at the edge rely on TSMC's N12e manufacturing processes and specialized semiconductor IP.The post How Synopsys IP and TSMC’s N12e Process are Driving AIoT appeared first on Chip Design....
May 2, 2024
I'm envisioning what one of these pieces would look like on the wall of my office. It would look awesome!...

featured video

Introducing Altera® Agilex 5 FPGAs and SoCs

Sponsored by Intel

Learn about the Altera Agilex 5 FPGA Family for tomorrow’s edge intelligent applications.

To learn more about Agilex 5 visit: Agilex™ 5 FPGA and SoC FPGA Product Overview

featured paper

Achieve Greater Design Flexibility and Reduce Costs with Chiplets

Sponsored by Keysight

Chiplets are a new way to build a system-on-chips (SoCs) to improve yields and reduce costs. It partitions the chip into discrete elements and connects them with a standardized interface, enabling designers to meet performance, efficiency, power, size, and cost challenges in the 5 / 6G, artificial intelligence (AI), and virtual reality (VR) era. This white paper will discuss the shift to chiplet adoption and Keysight EDA's implementation of the communication standard (UCIe) into the Keysight Advanced Design System (ADS).

Dive into the technical details – download now.

featured chalk talk

Achieving High Power Density with IGBT and SiC Power Modules
Sponsored by Mouser Electronics and Infineon
Recent trends in the inverter market have made high power density, scalability, and ease of assembly more important than ever before. In this episode of Chalk Talk, Amelia Dalton and Abraham Markose from Infineon examine how Easy & Econo power modules from Infineon can help solve common inverter design requirements. They explore the benefits and construction of these modules and how you can take advantage of them in your next design.
May 19, 2023