Elk Grove, Calif., March 19th, 2018 — Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced today the formation of a Proposed Working Group (PWG) to focus on defining security assurance requirements for IP.
“Our mission at Accellera is to provide a platform in which the electronics industry can collaborate to innovate and deliver global standards that improve design and verification productivity for electronics products,” stated Lu Dai, Chair of Accellera. “The new IP Security Assurance PWG aligns with our mission. In the past, security threats were mainly a concern of only certain market segments, but in today’s environment this is no longer the case. The concern and possibility for threats has expanded substantially, and the PWG will help to determine the interest and commitment in the industry for standardization in this area.”
“Currently there is no single standard to address security assurance in the development and delivery of IP to silicon integrators,” stated Martin Barnasconi, Accellera Technical Committee Chair. “If the PWG identifies interest in this area and the need to develop a standard, it will move forward to become a Working Group. We encourage everyone interested in creating an IP Security Assurance Specification to participate in our initial PWG kickoff meeting next month.”
The first IP Security Assurance Proposed Working Group meeting will be held Tuesday, April 17 from 10am – noon PT at Intel SC12, 3600 Juliette Lane, Santa Clara, CA 95054. Register for the meeting here. For more information about the PWG visit here.
Companies that are interested in this standardization topic and are active in EDA, design/verification of IP, and silicon integration are invited to participate in this PWG. Participants in the PWG need not be from Accellera member companies. Companies that have already showed interest in participating in the kickoff meeting include Cadence; Intel; Mentor, A Siemens Business; Sonics Inc.; Synopsys; and Qualcomm.
Background on IP Security Assurance Proposed Working Group
There is a certain level of risk when integrating third-party IP (3PIP) into Silicon. The risk stems from unknown behaviors that may occur once integrated, which could result as an exploitable vulnerability. Even if the source was provided, these unknowns may still exist since Integrators typically treat 3PIP as “black-box” technology. Silicon owners need a security assurance standard for acceptance before integrating 3PIP in order to minimize risk in their products. High-quality Silicon products are only such when they are built from high-quality IPs. The PWG will collect requirements, identify technical feasibility, identify industry interest and acceptance, and provide a recommendation to start or not start a Working Group.
About Accellera Systems Initiative
Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote and advance system-level design, modeling and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and, as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit www.accellera.org. Find out more about membership. Follow @accellera on Twitter or to comment, please use #accellera. Accellera Global Sponsors are: Cadence; Mentor, A Siemens Business; and Synopsys.
