industry news
Subscribe Now

Cadence Launches the Pegasus Verification System, a Massively Parallel Physical Signoff Solution

Highlights:

•       Delivers up to 10X improved performance across hundreds of CPUs for full-chip DRC signoff using foundry-certified rule decks to achieve 100 percent accurate results
•       Demonstrated near-linear scalability on up to 960 CPUs, reducing DRC signoff turnaround time from days to hours
•       Provides a flexible and elastic cloud-ready platform enabling customers to achieve aggressive time-to-market deadlines

SAN JOSE, Calif., April 11, 2017—Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the Pegasus™ Verification System, a massively parallel, cloud-ready physical verification signoff solution that enables engineers to deliver advanced-node ICs to market faster. The new solution is part of the full-flow Cadence® digital design and signoff suite and provides up to 10X faster design rule check (DRC) performance on hundreds of CPUs while also reducing turnaround time from days to hours versus the previous-generation Cadence solution. For more information on the Pegasus Verification System, visit http://www.cadence.com/go/pegasus.

Early adopters are already using the Pegasus Verification System for large-scale designs, across storage, high-performance computing, cloud, server and mobile applications. The solution offers customers the following benefits:

•       Massively parallel architecture: The solution incorporates a massively parallel architecture that provides unprecedented speed and capacity, enabling designers to easily run on hundreds of CPUs to speed up tapeout times.
•       Reduced full-chip physical verification runtimes: The solution’s gigascale processing offers near-linear scalability that has been demonstrated on up to 960 CPUs, allowing customers to dramatically reduce DRC signoff runtimes.
•       Low transition cost: Using existing foundry-certified rule decks, customers achieve 100 percent accurate results with a minimal learning curve.
•       Flexible cloud-ready platform: The solution offers native cloud support that provides an elastic and flexible compute environment for customers facing aggressive time-to-market deadlines.
•       Efficient use of CPU resources: The solution’s data flow architecture enables customers to optimize CPU usage, regardless of machine configurations and physical location, providing maximum flexibility to run on a wide range of hardware, achieving the fastest DRC signoff.

•       Native compatibility with Cadence digital and custom design flows: The Pegasus Verification System integrates seamlessly with the Virtuoso® custom design platform, delivering instantaneous DRC signoff checks to guide designers to a correct-by-construction flow that improves layout productivity. An integration with the Innovus™ Implementation System enables customers to run the Pegasus Verification System during multiple stages of the flow for a wide range of checks—signoff DRC and multi-patterning decomposition, color-balancing to improve yield, timing-aware metal fill to reduce timing closure iterations, incremental DRC and metal fill during engineering change orders (ECOs) that improve turnaround time, and full-chip DRC.

Texas Instruments (TI), an early Cadence Pegasus Verification System customer, was able to successfully scale the new solution with significant improvements. The Pegasus Verification System’s native cloud processing capabilities delivered improved turnaround times when compared with TI’s incumbent solution.

Additionally, Scott Barrick, senior manager of advanced engineering services at Microsemi Corporation (NASDAQ: MSCC) said, “As technology nodes advance, Microsemi is leveraging the Cadence Pegasus Verification System to shorten our time to tapeout. Its near-linear scalability can enable us to scale full-chip DRC runs to hundreds of CPUs for short periods and achieve up to 10 times the speedup when compared with the previous-generation Cadence solution. The next-generation solution offers native cloud support and gigascale processing, giving us the flexibility to add hundreds of CPUs for peak usage during tapeout while achieving our desired runtime.”

“Engineers have experienced increasing DRC complexity at advanced nodes, and current DRC solutions can’t support the turnaround requirements needed to ensure that design schedules are met,” said Dr. Anirudh Devgan, executive vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “The Pegasus Verification System’s innovative architecture and native cloud-ready processing provides an elastic and flexible computing environment, which can enable our customers to complete full-chip signoff DRC on advanced-node designs in a matter of hours, speeding time to market.”

The new Pegasus Verification System continues to extend the organic innovation within the Cadence digital design and signoff suite. The suite includes a comprehensive full flow from synthesis through implementation and signoff, offering the fastest path to achieve power, performance and area (PPA) targets across a wide variety of applications and vertical segments. The addition of the Pegasus Verification System to the full-flow suite also supports the company’s broader System Design Enablement (SDE) strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently.

About Cadence

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine’s 100 Best Companies to Work For. Learn more at cadence.comhttps://www.cadence.com/

7 thoughts on “Cadence Launches the Pegasus Verification System, a Massively Parallel Physical Signoff Solution”

  1. Pingback: Dungeon
  2. Pingback: cced.unila.ac.id
  3. Pingback: gvk biosciences
  4. Pingback: Kindertrampolin
  5. Pingback: casino games
  6. Pingback: check this

Leave a Reply

featured blogs
Aug 7, 2020
I love the clickety-clackety sounds of split flap displays, but -- in the case of this kinetic clock -- I'€™m enthralled by its sedately silent revolutions and evolutions....
Aug 7, 2020
HPC. FinTech. Machine Learning. Network Acceleration. These and many other emerging applications are stressing data center networks. Data center architectures evolve to ensure optimal resource utilization and allocation. PECFF (PCIe® Enclosure Compatible Form Factor) was dev...
Aug 7, 2020
[From the last episode: We looked at activation and what they'€™re for.] We'€™ve talked about the structure of machine-learning (ML) models and much of the hardware and math needed to do ML work. But there are some practical considerations that mean we may not directly us...
Aug 7, 2020
This is my second update post where I cover things that I have covered before, and where there is some news, but no enough to make a completely new post. The first update was Weekend Update .... [[ Click on the title to access the full blog on the Cadence Community site. ]]...

Featured Video

Are You Listening?

Sponsored by Mouser Electronics

Inspiration doesn’t stick to a schedule. Luckily, creativity is a natural stimulant. Let Mouser Electronics help you on your way.

More information

Featured Paper

Improving Performance in High-Voltage Systems With Zero-Drift Hall-Effect Current Sensing

Sponsored by Texas Instruments

Learn how major industry trends are driving demands for isolated current sensing, and how new zero-drift Hall-effect current sensors can improve isolation and measurement drift while simplifying the design process.

Click here for more information

Featured Chalk Talk

Embedded Display Applications Innovation

Sponsored by Mouser Electronics and Texas Instruments

DLP technology can add a whole new dimension to your embedded design. If you considered DLP in the past, but were put off by the cost, you need to watch this episode of Chalk Talk where Amelia Dalton chats with Philippe Dollo of Texas Instruments about the DLP LightCrafter 2000 EVM. This new kit makes DLP more accessible and less expensive to design in, and could have a dramatic impact on your next embedded design.

Click here for more information about Texas Instruments DLP2000 Digital Micromirror Device (DMD)