industry news
Subscribe Now

Agnisys Unveils Software to Automate Register Verification Process for SoC, IP, FPGA Designs

Lowell, MA. May 21, 2015 – Agnisys, Inc. announces immediate availability of ARV™ – Automatic Register Verification, an add-on product to IDesignSpec™, that enhances an already powerful register specification solution with capability to automate the register verification process for SoCs, IP and FPGA semiconductor projects. ARV saves semiconductor teams time and improves quality by enabling complete verification for design registers / memories that are the key integration point for semiconductor design, IP and software.

ARV comes in two configurations: ARV-Formal™ and ARV-Sim™
ARV-Formal is a complete solution that takes the register specification and RTL design as input and performs a formal proof to ensure all register operations conform to the specification. ARV-Formal is powered by 360-DV LaunchPad™, an adaptive formal technology platform from OneSpin Solutions that allows third-party companies with limited knowledge of formal technology to develop and deliver formal-based apps. It provides an automated, integrated flow that leverages the exhaustive nature of modern formal verification technology. ARV-Formal automatically generates assertions directly from the specification and executes them using the integrated formal engine, therefore completely automating setup and ensuring a very rapid return on investment. The formal engine is included as part of ARV-Formal, eliminating the need for an external formal product.

ARV-Sim is a complete register verification solution that integrates with Synopsys VCS®, Cadence Incisive® and Mentor Questa® simulators. ARV-Sim completely automates the UVM verification process. This approach eliminates the lengthy and error prone UVM test bench and sequence creation process. ARV-Sim provides the positive and negative sequences automatically – the actual test sequences that stimulate the hardware to ensure that the implementation is correct. ARV-Sim not only tests the register implementation but also the interface between the registers and the application logic.

Download the ARV Data Sheet

The Register Verification Challenge

Register verification is a significant part of the design verification problem. It is one of the first aspects of the design that must be tested because the rest of the semiconductor functionality depends on the accuracy of the register implementation. That is because registers contain the configuration setting of the hardware and is the basis of the hardware / software interface.

  • ARV Ensures the Register Implementation is Correct
  • ARV-Sim ensures that the coverage metrics are achieved. The only way to know you have tested all scenarios is by the coverage. ARV provides the coverage metrics and writes tests to enable 100% coverage on the registers.
  • ARV-Sim supports testing of special registers, for example, lock registers, shadow registers, register aliases, interrupts etc. It generates sequences for these special registers.
  • ARV-Sim ensures that the application logic correctly interfaces with the registers and memories.
  • Automatically creates register-focused coverage reports.
  • User can check either the IDesignSpec generated RTL code, the user’s own implementation, or a mix of the two with standard buses or user defined buses and transactions.
  • Being an add-on to IDesignSpec, users can import IP-XACT, SystemRDL, RALF, Word, Excel, CSV, XML and host of other formats.

The benefits of ARV at Allegro Microsystems
“All our new designs use Agnisys IDesignSpec for specification generation, automatic HDL generation and UVM register model generation for the register/memory blocks. This methodology enhancement has already brought much-needed consistency from common template based word document specifications, productivity and efficiency gains during the product development cycle across all projects. Our designs also have additional challenges that are not uncommon in the industry. For example, features like memory shadowing, aliasing, timers, customer locking and security,” said Khalid Chishti, Design Verification Manager, Allegro Micro Systems, LLC.

“These added features required us to spend time in the verification of these blocks since the UVM built-in library tests do not address these additional design features of the register blocks. In addition, it is hard to get adequate test coverage for the hardware updates of the registers in our system level test environment. Our digital designs strictly follow test plan and coverage based – Matrix Driven Verification (MDV) flow. To satisfy MDV flow, besides coding of the test benches, tests and models, the verification team had to write test plans, link them to a proper functional coverage matrix and then generate reports (Matrix report). The Agnisys ARV-Sim product provides a complete standalone verification solution for register/memory blocks that is completely turnkey and best of all; it requires no additional effort from the verification team to satisfy the MDV flow requirements,” Khalid added.

Download the Allegro Mictrosystems Success Story

Agnisys is uniquely positioned to create an advanced product like ARV-Formal and ARV-Sim because the company has many years of System Verilog and UVM experience, provides design and DV/UVM training and consulting services to semiconductor companies and has a track record for developing high quality design and verification software tools for the semiconductor industry.

ARV is available for immediate delivery:

ARV-Formal and ARV-Sim are add-on products to IDesignSpec. Engineering teams may request an ARV-Formal or ARV-Sim evaluation by completing the website form on the ARV product page. Also available is a detailed product datasheet and whitepaper. Access these downloads immediately from the Agnisys website on the ARV product page at (link to ARV product page) ARV-Sim and ARV-Formal are immediately available on Windows and Linux (Redhat and Ubuntu).
Reach out to Agnisys for pricing.

Request a Quotation

Agnisys at Design Automation Conference
Agnisys will demonstrate ARV-Formal and ARV-Sim and its entire register management and verification products at the 52nd Design Automation Conference (DAC) in Booth #2509 June 8-10 at the Moscone Center in San Francisco. Information about DAC can be found at: www.dac.com

About Agnisys

Agnisys, Inc., is focused on providing System Verilog and Universal Verification Methodology Products, Services and Training to Design Verification engineers. Agnisys enables semiconductor companies to increase productivity and proficiency while eliminating the design and verification errors in advanced System-on-Chip (SoC), Field Programmable Gate Array (FPGA) and Intellectual Property (IP) semiconductor designs. Agnisys Inc., established in 2007 in Massachusetts, develops and markets award winning and patented semiconductor design and verification tools.

Leave a Reply

featured blogs
Sep 29, 2020
I can easily see this kit at schools and in home-school settings. If I had an older kid or a young adult roaming around the house, I would jump at this little beauty....
Sep 29, 2020
About a year ago, we introduced the Spectre X simulator in the SPECTRE 19.1 base release. Since then, many enhancements have been made in Spectre X in the subsequent SPECTRE 19.1 ISR releases. The... [[ Click on the title to access the full blog on the Cadence Community site...
Sep 29, 2020
Our friends at DesignCon and Design News are launching the DesignCon Back-to-School webinar series.  Experts from DesignCon’s conference will share their insights from the electronics chip, board, and system industries, walking through use cases, defining various tools...
Sep 25, 2020
[From the last episode: We looked at different ways of accessing a single bit in a memory, including the use of multiplexors.] Today we'€™re going to look more specifically at memory cells '€“ these things we'€™ve been calling bit cells. We mentioned that there are many...

Featured Video

Four Ways to Improve Verification Performance and Throughput

Sponsored by Cadence Design Systems

Learn how to address your growing verification needs. Hear how Cadence Xcelium™ Logic Simulation improves your design’s performance and throughput: improving single-core engine performance, leveraging multi-core simulation, new features, and machine learning-optimized regression technology for up to 5X faster regressions.

Click here for more information about Xcelium Logic Simulation

Featured Paper

Designing highly efficient, powerful and fast EV charging stations

Sponsored by Texas Instruments

Scaling the necessary power for fast EV charging stations can be challenging. One solution is to use modular power converters stacked in parallel.

Learn More in our technical article

Featured Chalk Talk

Evaluation and Development Kits

Sponsored by Samtec

With signal integrity becoming increasingly challenging in today’s designs, interconnect is taking on a key role. In order to see how a particular interconnect solution will perform in our design, we really need hands-on evaluation of the technology. In this episode of Chalk Talk, Amelia Dalton chats with Matthew Burns of Samtec about evaluation and development kits for high-speed interconnect solutions.

More information about Samtec Evaluation and Development Kits