industry news
Subscribe Now

Synopsys Announces Immediate Availability of Broad Portfolio of Silicon-Proven IP for TSMC 16-nm FinFET Plus Processes

MOUNTAIN VIEW, Calif., April 7, 2015 /PRNewswire/ —

Highlights:

  • DesignWare Interface PHY IP portfolio for TSMC 16FF+ processes includes USB 3.0, 2.0 and HSIC; 16G PHY; PCI Express 4.0, 3.0 and 2.0; SATA 6G; HDMI 2.0; MIPI D-PHY; DDR4 and LPDDR4/3/2 IP
  • DesignWare Embedded Memories for the TSMC 16FF+ processes include high-speed, high-density and ultra high-density SRAM, Register File and ViaROM memory compilers
  • DesignWare STAR Memory System is optimized to provide high test coverage and efficient repair of FinFET-based memories

Synopsys, Inc. (Nasdaq:SNPS) today announced the availability of a broad portfolio of DesignWare® PHY IP for TSMC’s 16-nanometer (nm) FinFET Plus (16FF+) processes, enabling designers to integrate required functionality in mobile and enterprise system-on-chips (SoCs) with less risk. The silicon success of the DesignWare IP in TSMC’s 16FF+GL and 16FF+LL processes enables designers to accelerate the development of SoCs that incorporate embedded memories and interface IP for USB 3.0, 2.0 and HSICPCI Express® 4.0, 3.0 and 2.0; SATA 6G; HDMI 2.0; MIPI D-PHY; DDR4/3 and LPDDR4/3/2protocols on TSMC 16FF+ processes.

“TSMC’s long history of collaboration with Synopsys has provided designers with silicon-proven IP on advanced processes to speed development of SoCs for mobile and enterprise applications,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. “The availability of DesignWare IP for TSMC’s 16FF+ processes enables designers to benefit from the technology’s performance, power and area while accelerating their time-to-volume production.”

The DesignWare STAR Memory System® product is a comprehensive, integrated test, repair and diagnostics solution that supports Synopsys and third-party embedded memories. TSMC uses DesignWare STAR Memory System to characterize all of its 16FF+ memory compilers. The optimized test and repair algorithms maximize test coverage while reducing test time, lowering test cost and improving manufacturing yield. Synopsys also provides DesignWare Logic Libraries for the TSMC 16FF+ processes that include 7.5-, 9- and 10.5-track libraries, power optimization kits and High Performance Core (HPC) kits. All Synopsys embedded memories and logic libraries, including those on TSMC 16FF+ processes, work seamlessly with the IC Compiler™ IIplace-and-route system that accelerates throughput and improves quality of results.

“As the leading provider of physical IP for FinFET processes, Synopsys continues to invest in IP that helps designers take full advantage of the latest processes’ speed and power characteristics while implementing high-quality, proven IP in their SoCs,” said John Koeter, vice president of marketing for IP and prototyping at Synopsys. “Our close collaboration with TSMC mitigates risk for designers integrating interface, embedded memory and logic library IP into high-performance, low-power SoCs using TSMC’s 16FF+ process.”

Availability

The DesignWare USB 3.0 and 2.0, 16G PHY, PCI Express 4.0, 3.0 and 2.0, SATA 6G, HDMI 2.0, MIPI D-PHY, DDR4 multiPHY (including DDR4/3 and LPDDR4/3/2), logic library and embedded memory IP for TSMC’s 16FF+ process, as well as STAR Memory System and IC Compiler II, are available now.

About DesignWare IP

Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, complete interface IP solutions consisting of controller, PHY and next-generation verification IP, embedded processors and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys’ IP Accelerated initiative offers IP prototyping kits, IP software development kits and IP subsystems. Synopsys’ extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market. For more information on DesignWare IP, visithttp://www.synopsys.com/designware.

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world’s 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP, and is also a leader in software quality and security testing with its Coverity® solutions. Whether you’re a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest quality and security, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.

Leave a Reply

featured blogs
May 2, 2024
I'm envisioning what one of these pieces would look like on the wall of my office. It would look awesome!...
Apr 30, 2024
Analog IC design engineers need breakthrough technologies & chip design tools to solve modern challenges; learn more from our analog design panel at SNUG 2024.The post Why Analog Design Challenges Need Breakthrough Technologies appeared first on Chip Design....

featured video

MaxLinear Integrates Analog & Digital Design in One Chip with Cadence 3D Solvers

Sponsored by Cadence Design Systems

MaxLinear has the unique capability of integrating analog and digital design on the same chip. Because of this, the team developed some interesting technology in the communication space. In the optical infrastructure domain, they created the first fully integrated 5nm CMOS PAM4 DSP. All their products solve critical communication and high-frequency analysis challenges.

Learn more about how MaxLinear is using Cadence’s Clarity 3D Solver and EMX Planar 3D Solver in their design process.

featured paper

Designing Robust 5G Power Amplifiers for the Real World

Sponsored by Keysight

Simulating 5G power amplifier (PA) designs at the component and system levels with authentic modulation and high-fidelity behavioral models increases predictability, lowers risk, and shrinks schedules. Simulation software enables multi-technology layout and multi-domain analysis, evaluating the impacts of 5G PA design choices while delivering accurate results in a single virtual workspace. This application note delves into how authentic modulation enhances predictability and performance in 5G millimeter-wave systems.

Download now to revolutionize your design process.

featured chalk talk

Autonomous Robotics Connectivity Solutions
Sponsored by Mouser Electronics and Samtec
Connectivity solutions for autonomous robotic applications need to include a variety of orientations, stack heights, and contact systems. In this episode of Chalk Talk, Amelia Dalton and Matthew Burns from Samtec explore trends in autonomous robotic connectivity solutions and the benefits that Samtec interconnect solutions bring to these applications.
Jan 22, 2024
14,498 views