Altera Quartus II Software v14.1 Enables TFLOP Performance in Industry’s First FPGA with Hardened Floating Point DSP Blocks

San Jose, Calif., December 15, 2014 – Altera Corporation (Nasdaq: ALTR) today released itsQuartus® II software v14.1 featuring expanded support for Arria® 10 FPGAs and SoCs, the FPGA industry’s only devices with hardened floating point DSP blocks and the industry’s only 20 nm SoC FPGAs that integrate ARM processors. Altera’s latest software release provides immediate support for the hardened floating point DSP blocks integrated in Arria 10 FPGAs and SoCs. Users can choose between three unique DSP design entry flows and achieve up to an industry-leading 1.5 TFLOPS of DSP performance. The software also includes several optimizations that improve designer productivity by accelerating Arria 10 FPGA and SoC design time.

Integrated IEEE 754-compliant, floating-point DSP blocks in Arria 10 FPGAs and SoCs deliver unparalleled levels of DSP performance, designer productivity and logic efficiency. The Quartus II software v14.1 offers an advanced tool flow with multiple design entry options that target the hardened floating point DSP blocks and allow users to quickly design and deploy solutions that address a range of computationally intensive applications, in areas such as high-performance computing (HPC), radar and medical imaging. These design flows include OpenCL for software programmers, DSP Builder for model-based designers and hardware description language (HDL) flows for traditional FPGA designers. Unlike a soft implementation, hardened floating point DSP blocks do not consume valuable logic resources for floating point operations.

Additional Features in Quartus II Software v14.1 Include:

An enhanced Design Space Explorer II (DSE II) tool for faster timing closure, which delivers real-time status and reporting data to users. The data can be used to do side-by-side comparisons of multiple compiles being generated simultaneously on compute farms.
An optimized centralized IP catalog and improved graphical user interface (GUI) helps to store and easily find all custom IP in a single location.
Additional support for Altera’s new non-volatile MAX® 10 FPGAs, which feature dual-configuration flash, analog and embedded processing capabilities in a small-form-factor, low-cost, instant-on programmable logic device.
Enhancements to the JNEye serial link analysis tool further simplify board-level design and planning. The JNEye tool, along with Arria 10 silicon models, is able to simulate transmission line models and estimate insertion loss and cross talk parameters in Arria 10 designs.

Additional information about the latest features offered in Quartus II software v14.1 is available on the What’s New in Quartus II Software web page.

Pricing and Availability

Both the Subscription Edition and the free Web Edition of Quartus II software v14.1 are now available for download. Altera’s software subscription program consolidates software products and maintenance charges into one annual subscription payment. Subscribers receive Quartus II software, the ModelSim®-Altera Starter edition, and a full license to the IP Base Suite, which includes Altera’s most popular IP cores. The annual software subscription is $2,995 for a node-locked PC license and is available for purchase at Altera’s eStore.

About Altera

Altera® programmable solutions enable designers of electronic systems to rapidly and cost effectively innovate, differentiate and win in their markets. Altera offers FPGAs, SoCs, CPLDs and complementary technologies, such as power management, to provide high-value solutions to customers worldwide.