SAN JOSE, Calif. – December 2, 2014 – Calypto® Design Systems, Inc., a leader in low-power solutions and high-level design and verification, today launched the Catapult 8 platform, a third-generation, high-level synthesis (HLS) technology – the first in the industry.
Based on customer input that resulted in a multi-year development effort, the Catapult 8 platform is built on a completely revised architecture that speeds design and verification closure, enabling widespread adoption of HLS. The Catapult 8 platform with the new Configurable Hierarchical Design Architecture delivers:
- Control and predictability required to achieve design closure on complex designs
- Comprehensive design management and assembly systems with 10X capacity
- Integration with standard functional verification methodologies
- Power and verification optimized register-transfer level (RTL) code
- Native dual-language support of SystemC and C++
The Catapult 8 platform gives designers unprecedented control over which regions are optimized, and the ability to work “top down” or “bottom up,” which is required to integrate RTL intellectual property (IP). The new Catapult 8 database and smart caching techniques provide at least a 10X capacity improvement, making the synthesis of large subsystems possible. The synthesized RTL is now optimized for power and verification requirements, in addition to meeting area and performance constraints. Verification-optimized RTL is code that is ready to be deployed into industry and corporate standard verification flows, including flows based on universal verification methodology (UVM). In addition, the new architecture was expressly built to natively support both SystemC and C++ as input languages.
“With Catapult 8, we can now efficiently synthesize our multi-million gate data processing hardware,” said Emmanuel Liégeon, head of ASIC/FPGA Design Group at Thales Alenia Space France. “We write either C++ or SystemC, depending on the design and verification needs of each project, and then use Catapult’s configurable hierarchy technology, which makes it possible to synthesize much bigger designs.”
“Catapult 8 allows rapidly evolving C++ algorithms to be explored and optimized to meet our area, power and performance goals. With these capabilities and our successful experience with HLS, we have decided to migrate new IP development into synthesizable C++ to more efficiently reuse and retarget our IP,” said Michael Giovannini, hardware project leader in front-end team of Consumer Product Division for STMicroelectronics.
Need for Native Dual-language HLS Creating Verification and Power-optimized RTL
The selection of SystemC or C++ as the input language for HLS is driven by the design flow employed, as well as by some technical differences between the languages. As a result, it is becoming common for both languages to be used within a company. The new native dual-language capabilities for SystemC and pure C++ found in the Catapult 8 platform let companies standardize on a single HLS platform that meets the demands of different project teams.
RTL verification is a major pain point for system-on-chip (SoC) design; adopting a high-level synthesis and verification methodology alleviates some of the pain by speeding simulation by 1000x and accelerating verification and debug. The new Catapult 8 platform extracts design knowledge during synthesis, and optimizes the RTL to maximize verification coverage when running simulations derived from C++ or SystemC coverage tests. Using the Catapult GUI, the user can also relate RTL structures back to the C++ source, allowing them to write additional coverage tests when verification holes are identified. The result is that Catapult 8 dramatically cuts the cost of both functional coverage and structural coverage, enabling teams to achieve verification closure much faster.
Reducing power is becoming an essential design objective for many applications. Addressing low power requirements during high-level synthesis can provide significant power savings. Catapult 8 looks deeply through the design across clock boundaries, while the user explores alternative microarchitectures to determine optimal design solutions to achieve power, area, and performance goals.
“While second generation tools delivered excellent quality of results, some designers remained unconvinced they could use HLS. They needed extensive control for design closure, and better integration into standardized verification methodologies like UVM to fully achieve the verification benefits that HLS can provide,” said Sanjiv Kaul, president and CEO at Calypto. “Catapult 8 is the result of a major investment made by Calypto in HLS, during which we continued to enhance and support the previous generation of Catapult. Now with Catapult 8, the next generation of HLS is ready for widespread adoption into corporate standard design and verification flows, where engineering teams can benefit from access to our low power and enhanced SystemC capabilities.”
Available with the Catapult 8 platform is the new Catapult Catware library, an extensive source code library of synthesizable functions such as filters and FFTs, provided in SystemC and C++. Paramaterizable and easily configurable, Catapult Catware enables design team to quickly create highly effective design code for high-level synthesis. Both the Catapult 8 platform and Catapult Catware are available immediately.
Calypto® Design Systems is a leading provider of EDA software for high-level synthesis, RTL low power design, and formal verification. Calypto has offices in Europe, India, Japan, Korea, and North America with representation in China, Israel, and Taiwan.