industry news
Subscribe Now

Cadence Announces New Integrated Solution for Rapid Die-Package Interconnect Planning

SAN JOSE, Calif., May 21, 2014—Cadence Design Systems, Inc., a leader in global electronic design innovation, today announced a new integrated solution to significantly cut down die-package interconnect planning time by reducing iterations between silicon and package design teams. The solution, built on Cadence® OrbitIO™ technology, also shortens the time to converge on the physical interface between the die and package up to 60 percent, all within the context of the full system.

Building on its leadership position for co-design in the implementation stage, Cadence OrbitIO technology is used earlier in the design cycle to provide rapid interconnect planning of high-performance interfaces across multiple fabrics. As part of an overall co-design solution, Cadence OrbitIO technology provides seamless integration with Cadence SiP Layout and the Cadence Encounter® digital implementation platform. This integrated solution allows design teams to clearly communicate design intent throughout the flow, resulting in better decision-making, fewer iterations and shorter cycle-times. It can enable fabless semiconductor or systems companies to evaluate package route feasibility, and allows them to communicate a route plan to their package design resources, whether it is to an internal group or to an outsourced assembly and test (OSAT) provider.

“The Cadence OrbitIO global view of system connectivity helps Faraday reduce the time required to converge on the optimal die bump to package ball pad assignment,” said Dr. Wang-Jin Chen, senior technologist of Faraday. “The combination of connectivity optimization and route feasibility functions helped us produce a route plan resulting in two fewer package layers with all DDR signals implemented on a single package layer.”

To learn more about OrbitIO technology, please visit: www.cadence.com/products/sigrity/orbitio/pages/default.aspx

About Cadence

Cadence  (NASDAQ: CDNS) enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.

Leave a Reply

featured blogs
Oct 4, 2023
Explore why multi-die systems adoption calls for collaboration across the semiconductor industry w/ panel insights from EDA experts at Ansys, Bosch, & Intel.The post Industry Insights: How Collaboration Will Accelerate Adoption of Multi-Die Systems appeared first on Ch...
Sep 21, 2023
Not knowing all the stuff I don't know didn't come easy. I've had to read a lot of books to get where I am....

featured video

TDK PowerHap Piezo Actuators for Ideal Haptic Feedback

Sponsored by TDK

The PowerHap product line features high acceleration and large forces in a very compact design, coupled with a short response time. TDK’s piezo actuators also offers good sensing functionality by using the inverse piezo effect. Typical applications for the include automotive displays, smartphones and tablet.

Click here for more information about PowerHap Piezo Actuators

featured paper

Accelerating Embedded Software Development with the Intel® Simics® Simulator for Intel FPGAs

Sponsored by Intel

In a traditional FPGA design flow, the main portion of the software development cannot start until hardware is available. Intel provides the Intel Simics simulator for Intel Agilex 5 SoC FPGAs to give developers a vehicle to exercise their software in parallel with hardware development. Developers can run the same compiled binary software files providing the same results in the software’s execution. Software can be developed, debugged, and verified on the virtual platform up to a year in advance of the physical hardware becoming available.

Click here to learn more about the Intel Simics simulator

featured chalk talk

Solving Design Challenges Using TI's Code Free Sensorless BLDC Motor Drivers
Designing systems with Brushless DC motors can present us with a variety of difficult design challenges including motor deceleration, reliable motor startup and hardware complexity. In this episode of Chalk Talk, Vishnu Balaraj from Texas Instruments and Amelia Dalton investigate two new solutions for BLDC motor design that are code free, sensorless and easy to use. They review the features of the MCF8316A and MCT8316A motor drivers and examine how each of these solutions can make your next BLDC design easier than ever before.
Oct 19, 2022
40,394 views