EEJournal

industry news
Subscribe Now
April 11, 2014

New eBook explains faster parallel programming of memories via JTAG on manufacturing lines

Richardson, TX (April 9, 2014) ? Programming memory on the manufacturing line after the devices have been soldered to a circuit board must be accomplished quickly to keep pace with the assembly process. Unfortunately, the capacity of flash has gotten so large and the amount of data being programmed into them so extensive that the process has slowed considerably. 

A new eBook published by ASSET® InterTech (www.asset-intertech.com) explains how distributed architectures and on-board field programmable gate arrays (FPGA) accessed via JTAG can be deployed to accelerate in-line in-system programming (ISP) without jeopardizing the manufacturing beat rate. 

?Parallel programming ? or loading data into multiple circuit boards simultaneously ? speeds up the process by orders of magnitude,? said Kent Zetterberg, technical product manager for the ScanWorks® platform for embedded instruments. ?In addition, a programming engine can be temporarily inserted into an on-board FPGA to program multiple devices on the same board at the same time. When you start adding up all of the factors, you?ve got a really fast in-line programming process.? 

Titled ?Fast Flash Parallel In-System Programming?, the new eBook is available for free and can be downloaded from the eResources center on the ASSET website athttp://www.asset-intertech.com/Products/Boundary-Scan-Test/BST-Software/Fast-Flash-Parallel-In-System-Programming-ISP-JTAG 

Other informative eBooks, white papers and videos on issues relating to chip, board and system debug, validation and test can be downloaded from the ASSET website at: http://www.asset-intertech.com/eResources

About ASSET InterTech

ASSET InterTech is a leading supplier to the electronics industry of tools based on embedded instrumentation. Its SourcePoint debugger and the ScanWorks platform for embedded instruments overcome the limitations of external test and measurement equipment by applying instrumentation embedded in code and semiconductors to debug and validate software and firmware, and to perform design validation and manufacturing test on chips and circuit boards. ASSET’s recent acquisition of Arium (www.arium.com) added a powerful suite of firmware debug and trace tools to the ScanWorks platform. Designers can quickly debug firmware and then diagnose how it interacts with hardware. ASSET InterTech is located at 2201 North Central Expressway, Suite 105, Richardson, TX 75080. 

Leave a Reply

featured blogs
Celebrating World Intellectual Property Day
Apr 26, 2024
LEGO ® is the world's most famous toy brand. The experience of playing with these toys has endured over the years because of the innumerable possibilities they allow us: from simple textbook models to wherever our imagination might take us. We have always been driven by ...
More from Cadence...
Wow! Biomimetic LEDs!
Apr 26, 2024
Biological-inspired developments result in LEDs that are 55% brighter, but 55% brighter than what?...
More from Max's Cool Beans...
Want to Mix and Match Dies in a Single Package? UCIe Can Get You There
Apr 25, 2024
See how the UCIe protocol creates multi-die chips by connecting chiplets from different vendors and nodes, and learn about the role of IP and specifications.The post Want to Mix and Match Dies in a Single Package? UCIe Can Get You There appeared first on Chip Design....
More from Synopsys...

featured video

How MediaTek Optimizes SI Design with Cadence Optimality Explorer and Clarity 3D Solver

Sponsored by Cadence Design Systems

In the era of 5G/6G communication, signal integrity (SI) design considerations are important in high-speed interface design. MediaTek’s design process usually relies on human intuition, but with Cadence’s Optimality Intelligent System Explorer and Clarity 3D Solver, they’ve increased design productivity by 75X. The Optimality Explorer’s AI technology not only improves productivity, but also provides helpful insights and answers.

Learn how MediaTek uses Cadence tools in SI design

featured paper

Designing Robust 5G Power Amplifiers for the Real World

Sponsored by Keysight

Simulating 5G power amplifier (PA) designs at the component and system levels with authentic modulation and high-fidelity behavioral models increases predictability, lowers risk, and shrinks schedules. Simulation software enables multi-technology layout and multi-domain analysis, evaluating the impacts of 5G PA design choices while delivering accurate results in a single virtual workspace. This application note delves into how authentic modulation enhances predictability and performance in 5G millimeter-wave systems.

Download now to revolutionize your design process.

featured chalk talk

Digi XBee 3 Global Cellular Solutions
Sponsored by Mouser Electronics and Digi
Adding cellular capabilities to your next design can be a complicated, time consuming process. In this episode of Chalk Talk, Amelia Dalton and Alec Jahnke from Digi chat about how Digi XBee Global Cellular Solutions can help you navigate the complexities of adding cellular connectivity to your next design. They investigate how the Digi XBee software can help you monitor and manage your connected devices and how the Digi Xbee 3 cellular ecosystem can help future proof your next design.
Click here for more information about DIGI XBee® 3 Global LTE-M/NB-IoT Smart Modems
Nov 6, 2023
22,875 views