industry news
Subscribe Now

OneSpin Solutions Introduces Unique, Formal-Based Observation Coverage Solution to Magnify Verification Closure Precision

SANTA CLARA, CALIF. –– February 19, 2014 –– OneSpin Solutions™, provider of innovative formal assertion-based verification (ABV) and formal equivalence checking solutions, today announced Quantify™, patented software already proven in integrated circuit (IC) development environments to increase the precision with which verification coverage may be measured.

“While coverage measurement has been an essential element of the verification process, established methods have shortcomings that lead to the increased risk of post-production bugs and elongated engineering schedules,” says Dr. Raik Brinkmann, OneSpin Solutions’ president and chief executive officer (CEO). “Quantify represents a new approach that leverages formal technologies to provide a significantly more reliable mechanism for verification teams to get practical, measurable coverage metrics.”

Quantify leverages Observation Coverage, an effective metric that measures whether code changes in a design block will be caught by a specific verification environment. Its algorithm is efficient, rigorous and accurate, surpassing previous commercial offerings using a similar technique. Quantify also can analyze designs to pinpoint unreachable, redundant or dead code, or over-constrained design areas, as well as components that remain unreached, to identify simulation coverage issues.

The solution may be used to provide overall management coverage metrics to assess verification progress, and as a mechanism to identify and repair coverage holes during test development.

Verification Coverage

Verification coverage is a measurement of the progress of hardware verification based on the proportion of design code tested. The measure is commonly used to assess verification progress and to identify remaining untested areas in a design. A lack of adequate verification coverage indicates considerable risk of potential design problems.

Most commercial coverage tools focus on design code stimulation for simulation to ensure that areas of a design are activated during verification, but do not validate that a code error will be observed. Observation Coverage solves this issue by analyzing the reaction of the verification environment to code changes. However, existing Observation Coverage methods, based on either “Cone of Influence” (COI) or Mutation Analysis, can be inaccurate and require a significant amount of compute time.

Introducing Quantify

Quantify is a state-of-the-art coverage analysis technology and is used today in various verification flows with impressive results. It provides a number of accuracy and efficiency advantages over existing Control Coverage solutions, as well as other forms of Observation Coverage. Algorithms used by Quantify execute faster than those leveraged in other Observation Coverage-based solutions, and can be further accelerated through parallel operation.

As part of OneSpin 360 DV-Verify™ product line, Quantify augments the Assertion Based Verification formal engine to create a closed-loop, coverage-driven verification flow. It analyzes manual or automatically produced assertion sets against corresponding register transfer level (RTL) blocks and provides direction as to untested and untestable areas of the design, accelerating verification closure for these blocks. 

Quantify may also be used to provide control coverage information for simulation and formal environments. It will identify code that may not be reached and why during simulation and design areas that may be over-constrained in a formal environment. Quantify can be used as an independent coverage arbiter of environments using simulation and formal solutions supplied by other companies. Its general qualitative and quantitative measurements can quickly assess overall verification progress toward closure against a verification plan.

“We have seen some of our customers leverage OneSpin’s Quantify coverage technology with impressive results, providing a significant level of insight into their verification progress,” remarks Dr. Mike Bartley, CEO and founder of Test and Verification. “As we explore more effective verification management solutions through our asureSign™ tool, we expect to leverage the OneSpin technology to provide vital, timely feedback for this process.”

Quantify is easy to setup and use, and provides for an incremental use-model where coverage results from multiple runs may be merged. An Application Programming Interface (API) allows integration with coverage databases, such as Accellera’s Unified Coverage Interoperability Standard (UCIS), and verification management tools.

Quantify is shipping now as part of OneSpin 360 DV-Verify. Pricing is available upon request.

To learn more about OneSpin Solutions’ Quantify, visit: < >.

OneSpin at DVCon

Quantify and the entire OneSpin Product Family will be demonstrated in Booth #404 during DVCon Monday, March 3, from 5 p.m. until 7 p.m., and Tuesday and Wednesday, March 4-5, from 2:30 p.m. until 6 p.m. DVCon will be held at the DoubleTree Hotel in San Jose, Calif.

Information about DVCon can be found at: www.dvcon.org.

About OneSpin Solutions

Electronic design automation (EDA) supplier OneSpin Solutions was founded in 2005 as a spin-off from Infineon Technologies AG. Its award-winning formal verification software is based on more than 300 engineering years of development and application service experience. OneSpin’s comprehensive product line enables design teams to avoid costly design respins, while dramatically cutting their verification effort, costs and engineering schedules. Leading telecommunications, automotive, consumer electronics and embedded systems companies rely on OneSpin to achieve the highest possible verification quality while reducing their time-to-market pressures. Its United States headquarters is located in Santa Clara, Calif. Corporate headquarters is in Munich, Germany. Email: info@onespin-solutions.com. Website: www.onespin-solutions.com

Leave a Reply

featured blogs
Dec 2, 2021
Another six months have passed since we posted our last blog on Layout Verification. We are now happy to introduce some new videos around this topic especially around the next generation parasitic... [[ Click on the title to access the full blog on the Cadence Community site...
Dec 1, 2021
We discuss semiconductor lithography and the importance of women in engineering with Mariya Braylovska, Director of R&D for Custom Design & Manufacturing. The post Q&A with Mariya Braylovska, R&D Director, on the Joy of Solving Technical Challenges with a...
Nov 30, 2021
Have you ever wondered why Bill is a common nickname for William and Dick is a common nickname for Richard?...
Nov 8, 2021
Intel® FPGA Technology Day (IFTD) is a free four-day event that will be hosted virtually across the globe in North America, China, Japan, EMEA, and Asia Pacific from December 6-9, 2021. The theme of IFTD 2021 is 'Accelerating a Smart and Connected World.' This virtual event ...

featured video

Design Low-Energy Audio/Voice Capability for Hearables, Wearables & Always-On Devices

Sponsored by Cadence Design Systems

Designing an always-on system that needs to conserve battery life? Need to also include hands-free voice control for your users? Watch this video to learn how you can reduce the energy consumption of devices with small batteries and provide a solution for a greener world with the Cadence® Tensilica® HiFi 1 DSP family.

More information about Cadence® Tensilica® HiFi 1 DSP family

featured paper

4 questions to ask before choosing a Wi-SUN stack

Sponsored by Texas Instruments

Scalability, reliability, security, and speed—these are the advantages that the Wireless Smart Ubiquitous Network (Wi-SUN®) offers to smart cities and the Internet of Things. But as a developer, how can you maximize these advantages in your software design? In this article, TI addresses four questions to help you save development cost and get to market faster with a more streamlined design cycle for your IoT application.

Click to read more

Featured Chalk Talk

Easy Hardware and Software Scalability across Renesas RA MCUs

Sponsored by Mouser Electronics and Renesas

There are a bewildering number of choices when designing with an MCU. It can be a challenge to find one with exactly what your design requires - form factor, cost, power consumption, performance, features, and ease-of-use. In this episode of Chalk Talk, Amelia Dalton chats with Brad Rex of Renesas about the small-but-powerful Renesas RA family - a flexible and scalable collection of MCUs that may be exactly what your next project needs.

Click here for more information about Renesas Electronics RA Family Arm® Cortex® Microcontrollers