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Latest Release of Design Compiler Adds Technologies to Reduce Area and Accelerate Design Schedules

  • 10% reduction in area and leakage power at all process nodes
  • RTL analysis and cross-probing for faster debugging and creation of high-quality design data
  • Early congestion detection and optimization for faster design closure

The 2013.12 release of Synopsys’ Design Compiler® family, a key component of Synopsys’ Galaxy™ Implementation Platform, is now available. New innovations in this release reduce both design area and leakage power by 10 percent, while additional new capabilities accelerate design cycles by enabling faster debugging of design data and speeding design closure.

Design Compiler 2013.12 includes new optimizations that monotonically reduce design area by 10 percent on average while maintaining timing quality of results (QoR) at all process nodes. These area optimizations operate on new or legacy design netlists, with or without physical information. Utilizing these capabilities in conjunction with new congestion optimizations will allow customers to significantly reduce die area and ease design closure without impacting other QoR metrics.

New RTL Analysis capabilities include cross-probing between the RTL source and other design views such as schematic, timing reports and histograms, congestion and physical viewers. Additional RTL analysis capabilities analyze and report the number of logic levels for each timing path and RTL structures that are likely to cause routing congestion later in the flow. Users gain early visibility into potential timing and congestion issues and can create higher-quality RTL sooner.

New power optimizations reduce the use of leaky cells during RTL synthesis, resulting in 10 percent lower leakage power consumption and highly predictable leakage results. Also included is support for “golden” UPF (Unified Power Format), preserving the original power intent definition across the entire design flow as well as UPF support during design exploration. “Smaller die size and shorter design schedules continue to be key requirements for our customers designing at both established and emerging process nodes,” notes Bijan Kiani, vice president of marketing in Synopsys’ Implementation Group. “These new technologies for smaller design area, lower power consumption and advanced RTL analyses will help all our customers to become more competitive in their market segments, while strengthening Design Compiler’s position as the synthesis tool of choice for designers worldwide.”

Synopsys’ Design Compiler family maximizes productivity with its complete solution for RTL synthesis and test. Design Compiler Graphical uses advanced optimizations and shared technology with IC Compiler place-and-route to deliver best-in-class quality of results for the most challenging designs. In addition, it enables RTL designers to predict, visualize and alleviate routing congestion and to perform floorplan exploration prior to physical implementation. Design Compiler Graphical also produces physical guidance to IC Compiler that tightens timing and area correlation and speeds-up placement runtimes. Design Compiler Graphical is built upon DC Ultra™ synthesis that concurrently optimizes for timing, area, power and test and includes topographical technology to reduce costly design iterations.

DC Explorer, the newest addition to the Design Compiler Family, enables early RTL and floorplan exploration to accelerate synthesis and place-and-route. The Design Compiler family also includes: a synthesis-based test solution for the fastest, most cost-effective path to high-quality manufacturing tests and working silicon; and Formality® for equivalence checking. This best-in-class, production-proven solution is designed to achieve the industry’s fastest and most predictable RTL-to-GDSII flow.

Learn more about Design Compiler:
http://www.synopsys.com/Tools/Implementation/RTLSynthesis/Pages/default.aspx

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