Washington D.C., USA – December 10, 2013 – At this week’s IEEE International Electron Devices Meeting (IEDM 2013), imec reported the first functional strained germanium (Ge) quantum-well channel pMOS FinFETs, fabricated with a Si Fin replacement process on 300mm Si wafers. The device shows a possible evolution of the FinFET/trigate architecture for 7nm and 5nm CMOS technologies.
Since the 90nm technology, embedded SiGe source/drain has been a popular stressor method to produce strained Si that enhances pMOS devices. With diminishing device dimensions, the volume to implement stressors in the source and drain has also been severely scaled. Especially, with thin-body devices like FinFETs, the difficulty is even more pronounced. A possible relief would be to implement highly-strained material directly into the channel itself.
Imec’s solution, growing compressively strained Ge-channels on relaxed SiGe buffer, has already proven to boost the channel mobility, and is also known for its excellent scalability potential. The use of a fin replacement process to fabricate the strained Ge channel device makes it especially attractive for co-integration with other devices on a common Silicon substrate. The reported strained Ge p-channel FinFETs on SiGe trench buffer achieved peak transconductance (gmSAT )values of 1.3mS/µm at VDS=-0.5V with good short channel control down to 60nm gate length. The transconductance to subthreshold slope ratio of the devices (gmSAT/SSSAT)is high compared to published relaxed Ge FinFET devices.
Future developments will focus on improving the device performance through P-doping in the SiGe, optimizing Si cap passivation thickness on the Ge, and improving the gate wrap of the channel. “Unlike published Ge FinFETs, this work demonstrates a Ge-SiGe heterostructure-based quantum-well device in a FinFET form, which not only provides strain benefits but also enhancesshort-channel control,” remarked Nadine Collaert, program manager of the Ge/IIIV device R&D.
“Just recently, we reported the implementation of IIIV material into the device architecture using a fin replacement process,” stated Aaron Thean, director of the logic R&D program at imec. “This new achievement, implementing Ge into the channel through our fin replacement process, is another key ingredient to our menu of process possibilities for monolithic heterogeneous integration to extend CMOS and SOCs.”
Imec’s research into next-generation FinFETs is part of imec’s core CMOS program, in cooperation with imec’s key partners including Intel, Samsung, TSMC, Globalfoundries, Micron, SK Hynix, Toshiba/Sandisk, Panasonic, Sony, Qualcomm, Altera, Fujitsu, nVidia and Xilinx
Press release can be downloaded at http://www2.imec.be/be_en/press/imec-news/imecIEDMGepMOSFinFETs.html
About imec
Imec performs world-leading research in nanoelectronics. Imec leverages its scientific knowledge with the innovative power of its global partnerships in ICT, healthcare and energy. Imec delivers industry-relevant technology solutions. In a unique high-tech environment, its international top talent is committed to providing the building blocks for a better life in a sustainable society. Imec is headquartered in Leuven, Belgium, and has offices in Belgium, the Netherlands, Taiwan, US, China, India and Japan. Its staff of more than 2,000 people includes more than 650 industrial residents and guest researchers. In 2012, imec’s revenue (P&L) totaled 320 million euro. Further information on imec can be found at www.imec.be.
Imec is a registered trademark for the activities of IMEC International (a legal entity set up under Belgian law as a “stichting van openbaar nut”), imec Belgium (IMEC vzw supported by the Flemish Government), imec the Netherlands (Stichting IMEC Nederland, part of Holst Centre which is supported by the Dutch Government), imec Taiwan (IMEC Taiwan Co.) and imec China (IMEC Microelectronics (Shanghai) Co. Ltd.) and imec India (Imec India Private Limited).
