SAN JOSE, CA–(Marketwired – November 25, 2013) – Cadence Design Systems, Inc. (NASDAQ: CDNS)
Learn how to achieve faster design closure with physically-aware design knowledge at this year’s Front-End Design (FED) Summit. This day-long event will educate attendees on how to save design closure time and boost performance by incorporating knowledge of physically-aware design early into the front-end design implementation flow.
WHEN:
Thursday, December 5, 2013
WHERE:
Cadence Design Systems
Building 10 Auditorium
2655 Seely Ave.
San Jose, CA 95134
MORE ABOUT THE SUMMIT:
FED summit attendees will network with fellow logic designers and speak directly with Cadence® R&D experts about Encounter® RTL Compiler, Encounter Test, and Conformal® applications. At this day-long technical event, attendees will:
- Hear from design teams about the challenges they faced during logic synthesis, advanced low-power design and verification, engineering change order (ECO), and design-for-test (DFT) implementation, and the strategies they employed to address them
- Discover how best to achieve power, performance, and area goals on industry-leading IP cores
- Network, share your knowledge, and exchange best practices with your industry peers
For the full agenda, please click here.
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
