What: Learn how to close your safety critical design using the latest high-speed digital design and verification solutions from the leaders in high-speed interconnect, plus FPGA verification, at this complementary half-day technology network forum.  Network with other industry attendees during the event learn about their FPGA and PCB level signal integrity closure strategies.

Topics include:

• Anticipate SI issues on your high-speed digital PCBs using virtual prototypes and advanced channel simulation

• Closing the loop on DDR—reusing compliance test suites for both virtual and hardware prototypes

• Verification of High Speed Digital Designs for DO-254 Compliance

When:                  Dec. 5, 2013, half day seminar, 8:00 a.m.-1:30 p.m. 

Where:                 Agilent Technologies, Andover, Mass., for more information.

Additional

Information:          www.agilent.com/find/eesof.